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Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE
Long Form Data Sheet
PMC-980616
Issue 3
5 Gbit/s ATM Switch Fabric Element
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
DATASHEET
Released Issue 3: June 1999
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE
PMC-980616
Issue 3
5 Gbit/s ATM Switch Fabric Element
AAL1gator, AAL1gator2, Evil Twin Switching, QRT, QSE, and SATURN are trademarks of PMC-Sierra, Inc. AMCC is a registered trademark of Applied MicroCircuits Corporation. i960 is a registered trademark of Intel Corporation. National Semiconductor is a registered trademark of National Semiconductor Corporation. Vitesse is a trademark of Vitesse Semiconductor Corporation. All other brand or product names are trademarks of their respective companies or organizations.
U.S. Patents 5,557,607, 5,570,348, and 5,583,861
Copyright (c) 1999 PMC-Sierra, Inc. All Rights Reserved
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
PMC-980616
Issue 3
Public Revision History
Issue Number
Issue 1 Issue 2
Issue Date
March 1998 October 1998
Details of Change
Creation of Document Fixed all known typos/errors (e.g. wrong pinout: RAM_ADD(16) and RAM_PARITY swapped). Production Release Version
Issue 3
June 1999
(c) 1999 PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby BC Canada V5A 4V7 Phone: 604.415.6000 FAX: 604.415.6200
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Table of Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Multicast Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Diagnostic/Robustness Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 How the QSE Fits into Your System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.1 QSE System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.2 32 x 32 Switch Application (5 Gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 64 x 64 Switch Application (10 Gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4 5 Gbps to 20 Gbps Application Example - Seamless Growth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5 5 Gbps to 160 Gbps Application Example - LAN-to-WAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1 Phase Aligners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2 Data Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 Unicast Routing and Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4 Multicast Cell Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.1 Multicast Queue Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.2 Multicast Dequeue Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.6 BP_ACK Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.7 Interdevice Interconnectability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.8 Network Topologies and the Speedup Factor (SF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.8.1 Network Philosophy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8.2 Network Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8.3 Speedup Factor (SF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 External Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1 Switch Fabric Port and Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.1 SE_SOC Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1.2 Data Cell Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1.3 BP_ACK Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2 Data Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4 Multicast SRAM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5 Clocks and Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6 CTRL_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.7 STAT_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.8 Fabric Switch-Over . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
4
5
6
7 8
9
3.9 Cell Timing/Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 QSE Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.1 Distribution Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 Cell Start Offset Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.1 Relation Between External CELL_START and Local CELL_START . . . . . . . . . . . . . . . . . . . . . . 47 4.2.2 Relation Between Local CELL_START and Data Out of the QSE . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3 General Description of Phase Aligners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.4 Multicast Backpressure Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.5 Multilevel Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Fault Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5. 1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5. 2 Basic Data and BP/ACK Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5. 3 Fault Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5. 4 Interface Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5. 5 IRT-to-Switch Fabric Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5. 6 QSE Interface, Receive Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5. 7 QSE Interface, Transmit Data Direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5. 8 Switch Fabric-to-ORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5. 9 Types of Failures and Their Manifestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.2 Signal Locations (Signal Name to Ball) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3 Signal Locations (Ball to Signal Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.1 Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.2 Multicast RAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.3 QSE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4.4 Boundary Scan Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.5 Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.4.6 Total Pin Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.1 Microprocessor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.2 RAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3 QSE Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.4 Miscellaneous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Microprocessor Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.1 Microprocessor Ports Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.2 Note on Error Detection and Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.3 Microprocessor Ports Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.3.1 REVISION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.3.2 CHIP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
9.3.3 MULTICAST_GROUP_INDEX_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.3.4 MULTICAST_GROUP_VECTOR_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.3.5 MULTICAST_GROUP_OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.3.6 UC/MC_FAIRNESS_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.3.7 EXTENDED_CHIP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.3.8 MULTICAST_GROUP_INDEX_MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.3.9 INPUT_PORT_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.3.10 OUTPUT_PORT_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.3.11 INPUT_MARKED_CELLS_COUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.3.12 OUTPUT_MARKED_CELLS_COUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.3.13 PARITY_ERROR_PRESENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.3.14 PARITY_ERROR_LATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.3.15 PARITY_ERROR_INT_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.3.16 SE_INPUT_PORT_FAIL_PRESENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.3.17 SE_INPUT_PORT_FAIL_LATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.3.18 BP_ACK_FAIL_PRESENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.3.19 BP_ACK_FAIL_LATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.3.20 BP_REMOTE_FAIL_PRESENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3.21 BP_REMOTE_FAIL_LATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3.22 CONTROL_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3.23 INTERRUPT_STATUS_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3.24 MULTICAST_AGGREGATE_OUTPUT_AND_INPUT_MODES . . . . . . . . . . . . . . . . . . . . . . 105 9.3.25 UNICAST_AGGREGATE_OUTPUT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.26 SWITCH_FABRIC_ROW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.27 SWITCH_FABRIC_COLUMN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.28 CELL_START_OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.29 BP_CONTROL_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.30 ACK_PAYLOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.31 GANG_DEAD_ACK_PAYLOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.3.32 EXTENDED_SWITCH_MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 10 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.1 JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 10.2.1 Test-Logic-Reset: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.2.2 Run-Test-Idle: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.3 Capture-DR:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.4 Shift-DR: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.5 Update-DR: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.6 Capture-IR: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.7 Shift-IR: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.2.8 Update-IR: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.3 Boundary Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Released Datasheet
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
10.3.1 BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.3.2 EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.3.3 SAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.3.4 IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.3.5 STCTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.4 Boundary Scan Pin Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
List of Figures
Figure 1. QSE Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. QSE System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. 32 x 32 Switch Application (5 Gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. 64 x 64 Switch Application (10 Gbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5. 5 Gbps ATM Switch Using 8 QRTs, and 1 QSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. 10 Gbps ATM Switch Using 16 QRTs, and 2 QSEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. 20 Gbps ATM Switch Using 32 QRTs, and 4 QSEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. 5 Gbps to 160 Gbps Switches Modeled Using Only Two Cards . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. 5 Gbps ATM Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10. 10 Gbps ATM Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11. 15 Gbps ATM Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12. 20 Gbps ATM Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13. Basic QSE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14. Routing Bits Rotation for Unicast Traffic, Gang Mode of Four . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15. Example of Multicast Cell Handling in the QSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16. Ideal Distributed Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17. More Realistic Distributed Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 18. "Large" Distributed Network (Will not Work Well with Banyan Alone) . . . . . . . . . . . . . . . . 30 Figure 19. High-Level QRT/QSE System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 20. (3) x 1 - 5 Gbps System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 21. (5) x 4 - 20 Gbps System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 22. (1,3) x 1 - 10 Gbps System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 23. Randomizer (with Evil Twin Switching Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 24. Network Needs to be Run Faster than the Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 25. Definition of the Speedup Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 26. How to Use the SF to Select Favorable Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 27. SE_SOC Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 28. Expanded SE_SOC Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 29. BP_ACK Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 30. QSE Cell-Level Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 31. QSE Switch Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 32. Basic Forward and Backward Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 33. Basic Data Path (SE_D_OUT/IN and SE_SOC_OUT/IN in Forward Path, BP_ACK_OUT/IN in Backward Path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 34. 596-Ball Enhanced Plastic BGA Physical Dimensions Diagram (Top view) . . . . . . . . . . . . . 55 Figure 35. 596-Ball Enhanced Plastic BGA Physical Dimensions Diagram (Bottom view) . . . . . . . . . . . 56 Figure 36. QSE Pinout Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 37. Microprocessor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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PMC-980616 Figure Figure Figure Figure Figure Figure 38. 39. 40. 41. 42. 43.
Issue 3
RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSE Bit-Level Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TAP Controller Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
List of Tables
1. 2. 3. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. BP_CONTROL_REGISTER; Threshold Control Bits for Each Set of 32 Buffers . . . . . . . . . . . 25 Speedup Factor (1-Stage Networks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Speedup Factor (3-Stage Networks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Regular Cell Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PM73488 Mode Idle Cell Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Information Bit Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Failure Conditions, IRT-to Switch Fabric Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Failure Conditions, QSE Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Failure Conditions, QSE Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Failure Conditions, Switch Fabric-to-ORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Signal Locations (Signal Name to Ball) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Signal Locations (Ball to Signal Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Processor Interface Signals (21 Signal Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Multicast RAM Interface Signals (39 Signal Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 QSE Interface Signals (364 Signal Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Boundary Scan Signals (8 Signal Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Miscellaneous Signals (8 Signal Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Pin Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Estimated Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Microprocessor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 RAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 CTRL_IN, STAT_OUT, TEST_MODE and DEBUG Timing . . . . . . . . . . . . . . . . . . . . . . . . . 86 Valid Window Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Microprocessor Ports Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Boundary Scan Pin order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Standard Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
WAC-488-B
Issue 3
Product Overview
DESCRIPTION
The PM73488 (QSE) is an advanced communications device that enables the implementation of high performance switching systems. The QSE is a 32 x 32 cell based switch element, with a total sustainable bandwidth of 5 Gb/s. (The peak, or raw, bandwidth is much more than that: about 8 Gb/s). The QSE is designed to be used with other QSE's as part of a larger switch fabric. Various QSE combinations allow fabrics with theoretical peak capacities ranging from 5 Gb/s (one QSE) to 160 Gb/s. The QSE is not ATM specific; however, should the QSE be used for switching ATM cells, the QSE cell size is large enough to allow efficient direct mapping between QSE Cells and ATM cells. Multistage QSE Fabrics (Delta-Reverse Delta configuration) have rich connectivity with multiple paths between each source/destination pair. A QSE fabric performs cut-through unicast switching and uses Randomization and Evil-Twin algorithms to fully utilize these multiple paths and avoid the build up of internal hot spots. Randomization, in combination with multiple routing paths allows graceful degradation of QSE Fabric performance if internal links fail. To detect failed links, the QSE maintains and checks liveness patterns on input and output ports in hardware, and automatically routes around ports if they die. QSE data ports are 6 bits wide including a 4-bit wide 66 MHz data path, a one-bit wide start-of-cell indication, and a one-bit wide acknowledgment signal. Each port contains "Phase Aligners" to recover the clock for that port, thus removing the need to synchronize all data to a single global clock. When switching unicast traffic in a multistage fabric (one to three stages), the first nibble of the cell will come out of the last QSE stage before the last nibble of that cell enters the first stage. The cell thereby traverses the entire fabric in one cell time. If the cell sucessfully makes it to its destination, the ("egress") device accepting the cell from the last stage QSE has the opportunity to send a four bit "Ack Information Packet" back to source indicating what it did with this cell; at its simplest, the egress device can send back one pattern to indicate that the cell was accepted and another to indicate that the cell was dropped due to, say, buffer overflow. It is also possible that the cell was dropped inside the QSE fabric due to say a collision with another cell. The QSE classifies lost cells as due to one of three causes (collision, all possible outputs dead, or parity errors) and will generate an "Ack Information Packet" back to the source to communicate this event. In each QSE, the 4 bit pattern in the information packet can be independently software configured for each of the three cases. Note that since each QSE can be separately programmed, the patterns can even be setup so that the source knows where the cell was dropped. The information provided by the "Ack Information Packets" can be used by the device injecting cells into the first QSE stage to decide how to handle the cells; at its simplest, the device can resend cells that did not get through (a more sophisticated algorithm might also take into account where the cell was lost and the behavior of the evil twin algorithm to decide when to resend the cell; for example if the cell was dropped due to output congestion it might make sense to back off on cells to that output). For unicast traffic, part of switch bandwidth will be used to resend cells that did not make it through the first time around. This implies that sustained throughput is less than peak switching capacity. The amount of bandwidth required for resending cells and the effect of resending on latency and "Cell Delay Variation (CDV)" has been extensively studied with analytical models of the fabric. These results have then been cross checked with results from simulating software models of the fabric. This data is crucial for designing fabrics that can efficiently support
13
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
guaranteed "Quality of Service (QOS)" requirements. The recommended QSE fabric configurations for high quality switching takes these results into account; for example the 3 stage 160 Gb/s sustained throughput fabric has a peak capacity of 256 Gb/s (60% margin). The QSE fabric is store-and-forward for multicast traffic. Cell replication is performed in an optimal tree based manner where replication is done as far downstream as possible and each QSE contains cell buffers to buffer multicast cells. A multipriority backpressure feedback is used to control the flow of multicast cells through the fabric.
FEATURES
Switching Algorithm * * * * * * * * * * * * * * * * * * * * * Supports blocking resolution in the switch fabric. Guarantees a lower bound on switch performance using a patented randomization algorithm called Evil Twin Switching. Determines routes using specified bits in the header (self-routing switch fabric) for unicast traffic. Determines output groupings using a lookup table for multicast traffic. Allows output ports to be combined in groups of 1, 2, 4, 8, 16, or 32 for unicast traffic. Allows output ports to be combined in groups of 1, 2, or 4 for multicast traffic. Supports optimal tree-based multicast replication in the switch fabric. Supports 512 internal multicast groups, expandable to 256K with external SRAM. Provides 64 internal cell buffers for multicast cells. Checks the header parity. Counts tagged cells. Checks for connectivity and stuck-at faults on all switch fabric interconnects. Provides 32 switch fabric interfaces with integrated phase aligner clock recovery circuitry. Provides a Start-Of-Cell (SOC) output per four switch element interfaces. Provides an external 8-bit Synchronous SRAM (SSRAM) interface for multicast group expansion. Provides a demultiplexed address/data CPU interface. Provides an IEEE 1149.1 (JTAG) boundary scan test bus. 3.3 V supply voltage. 5 V tolerant inputs. 596-pin Enhanced Plastic Ball Grid Array (EPBGA) package. Operates from a single 66 MHz clock.
Multicast Support
Diagnostic/Robustness Features
I/O Features
Physical Characteristics
14
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616 Figure 1 shows a QSE system block diagram.
Issue 3
Multicast SSRAM (Optional)
SE_SOC_IN(0) Data from QRTs or QSEs Input Ports 0 NACK to QRTs or QSEs QSE PM73488 SE_SOC_IN(31) Data from QRTs or QSEs Input Ports 31 NACK to QRTs or QSEs
SE_SOC_OUT(0) Data to QRTs or QSEs Output Ports 0:3 NACK from QRTs or QSEs
SE_SOC_OUT(7) Data to QRTs or QSEs Output Ports 28:31 NACK from QRTs or QSEs Key: Host Interface Control or Data Signals Acknowledgment Signal
Figure 1. QSE Interface Block Diagram
15
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
1
HOW THE QSE FITS INTO YOUR SYSTEM
The QSE, together with the QRT, supports a wide range of high-performance ATM switching systems. These systems range in size from 5 Gbps to 160 Gbps. The systems can be developed to provide scalability with linear cost. Another key feature of the QSE/QRT architecture is that it is exceptionally fault-tolerant, both in the switch fabric and the UTOPIA interface. This section contains a quick overview of the QSE and several example applications: * * * * a 5 Gbps switch using PM73487s and a PM73488, a 10 Gbps switch using PM73487s and PM73488s, a switch architecture using PM73487s and PM73488s that scales from 5 Gbps to 20 Gbps, a switch architecture using PM73487s and PM73488s that scales from 5 Gpbs to 160 Gbps QSE System Overview
1.1
The QSE is switch element, combinations of which allows switch fabric implementations that span from 5 Gbps to 160 Gbps. The bandwidth of a single QSE is 5Gbps of sustainable bandwidth; the raw, or peak, bandwidth is 8Gbps. (Thus the QSE has an in-built speed-up factor of 8/5 = 1.6.) The QSE has 32 input ports and 32 output ports. Each port is a 66 MHz 6-bit interface, out of which 4 are data and 2 are control. Each port can be connected to another QSE or QRT. Figure 2 shows a QSE connected to a QRT.
Input Cell SDRAM Receive UTOPIA Level 2 Interface Physical and/or Adaptation Layers Control SSRAM Transmit UTOPIA Level 2 Interface Receive Feedback QRT (PM73487) Receive Nibble Data Transmit Nibble Data Transmit Feedback
Multicast SRAM
QSE (PM73488)
Output Cell SDRAM
Figure 2. QSE System Overview
16
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616 1.2 32 x 32 Switch Application (5 Gbps)
Issue 3
Figure 3 shows a basic 32 x 32 switch application (5 Gbps) using one QSE and eight QRTs.
622 Mbps Aggregate
QRT #1 (PM73487) Receive Input
x4
x4
QRT #1 (PM73487) Transmit Output
622 Mbps Aggregate
Receive UTOPIA Level 2 622 Mbps Aggregate QRT #8 (PM73487) Receive Input
x4
QSE (PM73488)
x4
Transmit UTOPIA Level 2 QRT #8 (PM73487) Transmit Output 622 Mbps Aggregate
Figure 3. 32 x 32 Switch Application (5 Gbps)
1.3
64 x 64 Switch Application (10 Gbps)
Figure 4 shows a 64 x 64 switch application (10 Gbps) using 6 QSEs and 16 QRTs. This application uses QSEs in a 3-stage fabric. This sized system can be implemented in a single 19 inch rack.
622 Mbps Aggregate Receive UTOPIA Level 2
QRT #1 (PM73487) Receive Input
x 4
x 4
QRT #1 (PM73487) Transmit Output
622 Mbps Aggregate Transmit UTOPIA Level 2
622 Mbps Aggregate
QRT #8 (PM73487) Receive Input
QSE (PM73488)
x 16
QSE (PM73488)
x 16
QSE (PM73488)
QRT #8 (PM73487) Transmit Output
622 Mbps Aggregate
622 Mbps Aggregate
QRT #9 (PM73487) Receive Input
QSE (PM73488)
x 16
QSE (PM73488)
x 16
QSE (PM73488)
QRT #9 (PM73487) Transmit Output
622 Mbps Aggregate
622 Mbps Aggregate
QRT #16 (PM73487) Receive Input
x
Receive UTOPIA Level 2
Transmit UTOPIA Level 2 QRT #16 (PM73487) Transmit Output 622 Mbps Aggregate
x
4
4
Figure 4. 64 x 64 Switch Application (10 Gbps)
17
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616 1.4
Issue 3
5 Gbps to 20 Gbps Application Example - Seamless Growth
Figure 5 illustrates the modularity of the QSE and QRT architecture. A 5 Gbps system can immediately be created (as shown in Figure 5), then be upgraded to 10 Gbps (as shown in Figure 6), or 20 Gbps (as shown in Figure 7 on page 19) with the QSE and the QRT. Since systems composed of the QSEs and QRTs are based on a single-stage switch fabric, the per-port cost for each system will remain the same.
Eight 155 Mbps Interfaces
Port Card * Two QRTs (PM73487s)
Eight 155 Mbps Interfaces
Port Card * Two QRTs (PM73487s) Switch Card * One QSE (PM73488s) Port Card * Two QRTs (PM73487s)
Eight 155 Mbps Interfaces
Eight 155 Mbps Interfaces
Port Card * Two QRTs (PM73487s)
Figure 5. 5 Gbps ATM Switch Using 8 QRTs, and 1 QSE
Eight 155 Mbps Interfaces
Port Card 1 * Two QRTs (PM73487s) Switch Card * One QSE (PM73488)
* * *
Eight 155 Mbps Interfaces Port Card 8 * Two QRTs (PM73487s)
Switch Card * One QSE (PM73488)
Figure 6. 10 Gbps ATM Switch Using 16 QRTs, and 2 QSEs
18
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Eight 155 Mbps Interfaces
Port Card 1 * Two QRTs (PM73487s)
Switch Card * One QSE (PM73488)
* * *
Eight 155 Mbps Interfaces Port Card 16 * Two QRTs (PM73487s)
Switch Card * One QSE (PM73488)
Switch Card * One QSE (PM73488)
Switch Card * One QSE (PM73488)
Figure 7. 20 Gbps ATM Switch Using 32 QRTs, and 4 QSEs
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Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616 1.5
Issue 3
5 Gbps to 160 Gbps Application Example - LAN-to-WAN
A powerful application of the QRT and QSE devices is the creation of modules that can be used in a range of switches with only the interconnection changing between different sizes. ATM switches from 5 Gbps to 160 Gbps can be realized with only two unique cards. A port card has one QRT, and a switch card has two QSEs. The switch fabric consists of three stages, each with 32 QSEs (or 16 switch cards). To plan for future scalability, the middle stage must be built-in upfront. This is a one-time cost. Then, in order to scale in 5 Gbps increments, one switch card and its accompanying eight port cards should be added. Finer bandwidth scaling is possible by populating the additional switch card with port cards as needed (in increments of 622 Mbps). With this switch fabric topology, scaling is possible up to 160 Gbps. Once the initial middle stage cost has been incurred, the per-port cost for 5 Gbps through 160 Gbps systems remains constant
Port Card - One QRT One UTOPIA Level 2 Interface QRT (PM73487)
Switch Card - Two QSEs x32 QSE (PM73488) x32 x32 QSE (PM73488) x32
Figure 8. 5 Gbps to 160 Gbps Switches Modeled Using Only Two Cards
20
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
622 Mbps
Port Card #1 Rx Input Port Card #8 Rx Input
622 Mbps
Switch Card #17 Stage 1 QSE x2 Switch Card #1
Switch Card #17 Stage 3 QSE x2
Port Card #1 Tx Output Port Card #8 Tx Output
622 Mbps
622 Mbps
Switch Card #2
Switch Card #16
Figure 9. 5 Gbps ATM Switch
Figure 9 shows a 5 Gbps ATM switch using 8 port cards (8 QRTs) and 17 switch cards (34 QSEs). The middle stage is composed of 16 switch cards. The 5 Gbps bandwith is achieved by adding switch card #17 (which is depicted using two boxes: one stage 1 QSE and one stage 3 QSE), and eight port cards (each of which is depicted using two boxes: one for the Rx input side, and one for the Tx output side). Lines between stage 1 and stage 2, and stage 2 and stage 3 switch cards represent two sets of wires, one to each of the QSEs in the middle stage switch cards.
21
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Figure 10 shows a 10 Gbps ATM switch using 16 port cards (16 QRTs) and 18 switch cards (36 QSEs). Here, another switch card and eight port cards have been added to the 5 Gbps switch depicted in Figure 9.
622 Mbps 622 Mbps
Port Card #1 Rx Input Port Card #8 Rx Input Port Card #9 Rx Input Port Card #16 Rx Input
622 Mbps
Switch Card #17 Stage 1 QSE x2 Switch Card #1 Switch Card #18 Stage 1 QSE x2
Switch Card #17 Stage 3 QSE x2
Port Card #1 Tx Output Port Card #8 Tx Output Port Card #9 Tx Output Port Card #16 Tx Output
622 Mbps
622 Mbps
622 Mbps
622 Mbps
Switch Card #18 Stage 3 QSE x2
622 Mbps
Switch Card #2
Switch Card #16
Figure 10. 10 Gbps ATM Switch
22
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Figure 11 shows a 15 Gbps ATM switch using 24 port cards (24 QRTs) and 19 switch cards (38 QSEs).Here, once again, another switch card and eight port cards have been added
622 Mbps
Port Card #1 Rx Input Port Card #8 Rx Input Port Card #9 Rx Input Port Card #16 Rx Input Port Card #17 Rx Input Port Card #24 Rx Input
622 Mbps
Switch Card #17 Stage 1 QSE x2 Switch Card #1 Switch Card #18 Stage 1 QSE x2
Switch Card #17 Stage 3 QSE x2
Port Card #1 Tx Output Port Card #8 Tx Output Port Card #9 Tx Output Port Card #16 Tx Output Port Card #17 Tx Output Port Card #24 Tx Output
622 Mbps
622 Mbps
622 Mbps
622 Mbps
622 Mbps
Switch Card #18 Stage 3 QSE x2
622 Mbps
622 Mbps
622 Mbps
622 Mbps
Switch Card #19 Stage 1 QSE x2 Switch Card #2
Switch Card #19 Stage 3 QSE x2
622 Mbps
Switch Card #16
Figure 11. 15 Gbps ATM Switch
23
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Figure 12 shows a 20 Gbps ATM switch composed of 32 port cards (32 QRTs) and 20 switch cards (40 QSEs). By adding additional sets of a switch card and eight port cards in the same manner, this system can scale up to 160 Gbps.
622 Mbps
Port Card #1 Rx Input Port Card #8 Rx Input Port Card #9 Rx Input Port Card #16 Rx Input Port Card #17 Rx Input Port Card #24 Rx Input Port Card #25 Rx Input Port Card #32 Rx Input
622 Mbps
Switch Card #17 Stage 1 QSE x2 Switch Card #1 Switch Card #18 Stage 1 QSE x2
Switch Card #17 Stage 3 QSE x2
Port Card #1 Tx Output Port Card #8 Tx Output Port Card #9 Tx Output Port Card #16 Tx Output Port Card #17 Tx Output Port Card #24 Tx Output Port Card #25 Tx Output Port Card #32 Tx Output
622 Mbps
622 Mbps
622 Mbps
622 Mbps
622 Mbps
Switch Card #18 Stage 3 QSE x2
622 Mbps
622 Mbps
622 Mbps
622 Mbps
Switch Card #19 Stage 1 QSE x2 Switch Card #2 Switch Card #20 Stage 1 QSE x2
Switch Card #19 Stage 3 QSE x2
622 Mbps
622 Mbps
622 Mbps
622 Mbps
Switch Card #20 Stage 3 QSE x2
622 Mbps
Switch Card #16
Figure 12. 20 Gbps ATM Switch
24
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
2
THEORY OF OPERATION
Multiple PM73488 QSEs can be combined to build a scalable switch fabric. The QSE switches data in the form of 118 nibble cells. The QSE has 32-input ports and 32 output ports, each containing a nibble-wide data interface, an SOC signal, and a backpressure/data-acknowledge signal. Groups of 1, 2, 4, 8, 16, or 32 ports can be internally configured to act as a single aggregate port (also called gang) for unicast traffic. For multicast traffic, inputs and outputs can be grouped together in groups of 1, 2, or 4 ports. The input multicast grouping mode, output multicast grouping mode, and the unicast grouping modes do not need to be the same. Also, the QSE can be configured as a single 32 input x 32 output switch The cell flow through the QSE has two separate data paths; one path for unicast cells and another path for multicast cells. Unicast cells are routed from one end of the switch fabric to the other end in a single cell time. In other words, no unicast cells are ever stored in the switch fabric. Unicast cells are stored only at the ingress and egress of the switch fabric. Multicast cells are routed in a store-and-forward manner. Each QSE can store up to 64 multicast cells. The QRT used as an interface to a switch fabric constructed with QSEs allows the construction of an ATM switch up to 160 Gbps. A diagram of the QSE cell flow is shown in Figure 13. The unicast cell flow contains a routing stage that uses routing information from the cell header to determine the output group. The multicast cell flow contains an interface to an external SSRAM that contains the Multicast Port Vector (MPV) information for routing cells to multiple output groups.
Forward Cell Flow Backpressure/Ack Flow Miscellaneous Signals External SSRAM
Phase Aligners and Receive SE_D_IN and SE_SOC_IN
Multicast Path Data Drivers Arbiter
BP_ACK Drivers Unicast Routing and Distribution Path
Phase Aligners and Receive BP_ACK_IN
Figure 13. Basic QSE Flow
25
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616 2.1 Phase Aligners
Issue 3
Phase aligners aid in constructing large systems. Clock information is recovered from the data sent to each QSE switch fabric port. Phase aligners are used on the BP_ACK_IN(31:0), SE_SOC_IN(31:0), and SE_D_IN(31:0, 3:0) signal lines. Since there is no setup or hold time requirements on these signals, the overall clock distribution scheme within the system can be simplified. However, overall system jitter and skew between signals on the same switch fabric data port must still be managed. 2.2 Data Drivers
Another aid to constructing large systems is an elastic store at each QSE input data port. The data elastic store allows data arriving from different ports to be offset by up to a maximum of eight clock cycles. The internally generated and software programmable local CELL_START signal marks the end of an 8-clock-period window within which the SOC marker on each of the SE_SOC_IN(31:0) lines must arrive. 2.3 Unicast Routing and Distribution
Each of the 32 nibble-wide inputs is connected to an output by a crossbar. This crossbar is transparently controlled by the cell's routing tag, which specifies the input-to-output connection. In the event of a conflict for an output port, higher priority cells are given preference over lower priority cells. There are three unicast cell priorities: high, medium, and low. The gang of 32, also known as distribution mode, is a special unicast routing mode in which incoming unicast cells are routed to outputs using PMC's patented congestion-minimization (Evil Twin Switching) algorithm. In this mode, no routing information is used from the cell's routing tag. Depending on the gang mode, the QSE will need a number of routing bits to determine the output gang of a unicast cell. For example, in gang mode of four, there are eight output gangs, thus three routing bits are required for selecting the QSE. However, in distribution mode no routing bits are needed. The routing bits are taken from the head of the routing tag and are then shifted back in at the tail (which preserves header parity). This allows the next set of routing bits to be always accessible at the same spot in the tag, namely the head. The cell routing tag is broken into eight nibbles, namely TAG_0 through TAG_7. Figure 14 on page 27 shows the tag rotation for gang mode of four (three routing bits are used by the QSE from TAG_0 and then shifted back in at the tail of TAG_7). TAG_0 is broken up and part of it ended up at the end of TAG_7 (shown by the white area in Figure 14 on page 27). As a result, all the other tags (TAG_1 through TAG_7) also get broken up and shifted (as shown by the light and dark gray areas of Figure 14 on page 27).
26
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
3210 TAG_0 TAG_1 TAG_2 TAG_3 TAG_4 TAG_5 TAG_6 TAG_7
Bit Mapping
3210 TAG_0 TAG_1 TAG_2 TAG_3 TAG_4 TAG_5 TAG_6 TAG_7
Figure 14. Routing Bits Rotation for Unicast Traffic, Gang Mode of Four
2.4
Multicast Cell Flow
There are 64 internal cell buffers for multicast traffic. These buffers are shared among three multicast priorities: high, medium, and low. These 64 buffers are grouped into two sets of 32-cell buffers each. One set is dedicated to ports 0 to 15, the other set to ports 16 to 32. A multicast queue engine dynamically allocates the cell buffers to incoming multicast cells. Each cell is buffered until it can be sent out on all output ports to which it should be routed. These output ports are designated by a Multicast Group Vector (MGV) that is associated with a Multicast Group Index (MGI) carried by each multicast cell. Each QSE holds multicast MGVs in an MGV RAM. The QSE has internal RAM to support up to 128 MGVs. This support can be extended up to 256K MGVs by using an external MGV RAM. Each multicast cell contains the RAM address of the MGV it is supposed to use. When a multicast cell is received, its MGV is fetched from RAM and copied to the MULTICAST_QUEUE_COMPLETION register. The MULTICAST_QUEUE_COMPLETION register tracks to which QSE ports the cell needs to be sent before its cell buffer can be cleared. In a multistage QSE fabric, each multicast cell will look up MGVs at each QSE. The MGV's sequence determines which output ports will finally receive the cell. The MGV structure allows software to create an optimal distribution tree for each multicast cell. Multicast operation can be best understood by considering the QSE multicast path as two separate engines; the multicast queue engine and the multicast dequeue engine. The multicast queue engine queues cells into the multicast cell buffers (of which there are 64), and issues backpressure on the BP_ACK_OUT(31:0) lines. The multicast dequeue engine selects and dequeues cells from the buffers for output ports as guided by the backpressure received on the BP_ACK_IN(31:0) lines.
27
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616 2.4.1 Multicast Queue Engine
Issue 3
The multicast queue engine associates input ports with cell buffers, computes backpressure for the input ports, and stores incoming cells into the buffers. In doing so, it guarantees: * * * No input port will have more than three cells pending in the QSE -- this can be changed to allow four pending cells by setting the "Allow 4 Bits Per Port" bit (bit 1) in the BP CONTROL register. No input port will have more than two high-priority cells pending. The sum of low- and medium-priority cells pending from any single input port will be less than 2.
In addition, the queue engine allows buffers to be reserved for high-priority cells or high/medium-priority cells. This is controlled by bits 2 and 3 of the BP_CONTROL_REGISTER (refer to section 9.3.29 "BP_CONTROL_REGISTER" on page 109). The four possible combinations for these two bits are listed in Table 1. The multicast queue engine will compute backpressure for the preceding QSE/QRT to ensure the constraints listed in Table 1 are satisfied. The same reservation policy applies to both sets of 32 buffers.
Table 1. BP_CONTROL_REGISTER; Threshold Control Bits for Each Set of 32 Buffers Bit 3 0 Bit 2 0 Description * Four buffers are reserved for high-priority cells. * Four buffers are reserved for high- or medium-priority cells. * All other buffers can be used by any cell. * Four buffers are reserved for high-priority cells. * All other buffers can be used by any cell. * Eight buffers are reserved for high- or medium-priority cells. * All other buffers can be used by any cell. * All buffers can be used by any cell.
0 1 1
1 0 1
After the MGV address for the cell enters the QSE, the MGV associated with that cell is fetched and loaded into the QUEUE_COMPLETION_REGISTER (an internal register) as soon as possible. 2.4.2 Multicast Dequeue Engine
In each cell time, the multicast dequeue engine selects one multicast cell for each of the 32 output ports. In effect, all multicast cells wanting to go to a particular output port arbitrate among themselves to select the most appropriate port. Arbitration occurs independently for all 32 ports. The cells winning the internal multicast arbitration then compete with the incoming unicast cells for access to the output ports. Multicast arbitration winners are chosen to satisfy the following conditions in this sequence: * * * * * * Obey backpressure from the down stream QSE or QRT. Only cells with the allowed priorities will take part in arbitration. Higher priority cells win over lower priority cells. Cells that came in earlier win over cells that came in later (if they have the same priority). If multiple cells have the same priority and came in simultaneously, cells from a random input gang group will be selected. If multiple cells have the same priority, came in simultaneously, and belong to the same input gang group, the cell with the lowest port number will be selected. Ties are broken randomly.
28
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
This arbitration occurs among all cells in the cell buffers and occurs for all 32 ports. In effect, arbitration occurs for output ports in sequence, starting with cells arbitrating for port 0, then for port 1, and continuing on until port 31 (even though the actual implementation uses a parallel algorithm). Multicast cells that have won this arbitration then compete with unicast cells for access to the output ports. In this contention, the cell with the highest priority wins and ties are broken randomly according to the programmable ratio set in the UC/MC_FAIRNESS_REGISTER (refer to section 9.3.6 "UC/MC_FAIRNESS_REGISTER" on page 97).
All these operations are optimized so that, in the absence of congestion, it is possible for a multicast cell to leave the QSE in the cell time immediately after it arrived. As mentioned before, the queue completion register (32-bit vector) indicates the outputs to which each multicast cell needs to go. As a cell goes out on its desired outputs, the appropriate bits in the queue completion register are cleared. When all bits in the queue completion register have been cleared, the cell is deleted from the internal buffers and the buffer is reused for new incoming traffic.
29
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Figure 15 shows an example of a high-priority cell preempting a cell in the multicast queue, and the resulting bit settings in the MULTICAST_QUEUE_COMPLETION_REGISTER (an internal register). (For the sake of simplicity, only 8 of the 32 outputs, and eight bits of the MGV_REGISTER (refer to section 9.3.4 "MULTICAST_GROUP_VECTOR_REGISTER" on page 96) and MULTICAST_GROUP_COMPLETION_REGISTER (an internal register) are shown.)
Multicast Group Vector (MGV) (Specifies where cells should be sent.)
High-Priority Cell CELL_H
Output(0)
Output(1)
Multicast Queue CELL_M Output(2) CELL_M
MULTICAST_QUEUE_COMPLETION_REGISTER (Records if the cells arrived at the destinations indicated in the MULTICAST_GROUP_VECTOR_REGISTER.)
0 0 1 1 0 1 0 7 0 7 0
0 0 1 0 0 1 0 0
0
Output(3) CELL_H
Output(4)
Output(5) CELL_M
Output(6) This bit is not set since a higher priority cell was output on Output(3), preempting the cell in the multicast queue.
Output(7)
Figure 15. Example of Multicast Cell Handling in the QSE
2.5
Arbiter
The arbiter selects between unicast cells and multicast cells contending for the same output port. Higher priority cells are given preference over lower priority cells. If a multicast cell and unicast cell have the same priority, one cell is randomly chosen. The random choice can be biased in favor of either unicast cells or multicast cells at different points in the switch fabric by using the UC/MC_FAIRNESS_REGISTER (refer to section 9.3.6 "UC/ MC_FAIRNESS_REGISTER" on page 97). In general, unicast cells should be favored at later stages in the switch fabric. Favoring unicast cells is necessary in multiple-stage switch fabrics since unicast cells are routed in a cutthrough fashion and multicast cells are routed in a store-and-forward fashion. As such, a unicast cell becomes more "valuable" as it proceeds further in the switch fabric, since it did so at the expense of other cells.
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PMC-980616
Issue 3
For example, consider a congested 3-stage switch fabric where unicast cells and multicast cells of equal priorities collide at each stage in the fabric, without any biasing. A unicast cell must make it from ingress to egress in one cell time and the chances of doing so would be a little more than (1/2)3 = 12.5%. However, each multicast cell would have a 50% chance of advancing to the next stage in the switch fabric. 2.6 BP_ACK Drivers
The BP_ACK_OUT(31:0) lines are used to send information from a QSE to upstream QSEs or QRTs. These lines are used to send two types of information: * * Backpressure information (for unicast cells). Transmit acknowledge information (for multicast cells).
Backpressure information is sent for multicast cells. This information indicates to an upstream QRT or QSE if the QSE can accept another multicast cell in the next cell time. Backpressure information also indicates what multicast cell priorities the QSE can accept. Cell transmit acknowledge information is sent for unicast cells. This information signals whether or not the unicast cell transmitted in the current cell time made it to its destination QRT. If the cell makes it to the destination QRT, an Acknowledgment (ACK) is sent. If the cell has been dropped in the switch fabric, information is sent back indicating if the cell was dropped internally Mid Switch Negative Acknowledgment (MNACK) or at the output of the switch fabric Output Negative Acknowledgment (ONACK). The MNACK and ONACK is used by the QRT to determine when to retry sending the given cell. 2.7 Interdevice Interconnectability
All input and output ports can be configured in groups of four to directly connect to either QRT devices or other QSE devices. This allows considerable flexibility in the switch fabric types and sizes that can be constructed using the entire PMC chip set. 2.8 Network Topologies and the Speedup Factor (SF)
For many switch fabric architectures using the QSE, a single metric called the Speedup Factor (SF) allows comparison of different network topologies, which is independent of traffic load and type. The SF also allows for predictions about the network performance. Before describing the SF metric, we will briefly discuss the network philosophy and the different network topologies.
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PMC-980616 2.8.1 Network Philosophy
Issue 3
Given current technology, to scale through 160 Gbps, a network must be distributed and use buffers at the network inputs and outputs. In an ideal world, crossbars of any arbitrary size could be built to provide connectivity for the network inputs and outputs. Additionally, there would be a central "brain", or global arbiter, to control the input buffers and schedule cells optimally for routing in the network, as shown in Figure 16.
Global Arbiter
"Perfect Crossbar"
Input Buffers
Output Buffers
Figure 16. Ideal Distributed Network
Unfortunately, given real constraints, it is not possible to have a global arbiter wired to each input that has knowledge of all cells in the system, and can quickly make optimal decisions about routing. Thus, each input must make decisions using knowledge local to its buffers. This results in the possibility of collisions at the network outputs, even though it is a "perfect" crossbar, as shown in Figure 17.
Output Collision
Local Arbiters "Perfect Crossbar"
Input Buffers
Output Buffers
Figure 17. More Realistic Distributed Network
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PMC-980616
Issue 3
Replacing the idealized crossbar with a buildable, traditional Banyan network increases the possibility of internal network collisions, as shown in Figure 18. Given a particular Banyan network, one can always find a large class of traffic patterns that will cause many internal collisions. For large Banyan networks, the collision problem is greatly increased.
Internal Collisions
Output Collision
Local Arbiters Banyan
Input Buffers
Output Buffers
Figure 18. "Large" Distributed Network (Will not Work Well with Banyan Alone)
To reduce internal collisions in the traffic-dependent Banyan networks, the QRT/QSE network adds a distribution/ randomizing network (shown in Figure 19) that uses a patented intelligent configuration algorithm, known as Evil Twin Switching. The algorithm (described in section 2.8.3 "Speedup Factor (SF)" on page 36) allows lower-bounding the network performance, independent of traffic patterns.
Internal Collisions
Local Arbiters
Intelligent Configuration Algorithm Banyan and Randomizer
Input Buffers
Output Buffers
Figure 19. High-Level QRT/QSE System
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PMC-980616
Issue 3
To overcome the inefficiencies caused by collision in the network, the fabric must be run at a rate greater than line rate. The speedup factor is the minimum rate necessary to guarantee that the network is no longer the system bottleneck. Note that in this case, the network efficiently moves data from the input to the output buffers, and the switch performs similar to a purely output buffered switch. 2.8.2 Network Definition
A large range of switch fabrics can be described as follows: with the following notation: "p" refers to the number of fabric planes, and "x," "y," and "z" refer to the routing tag size necessary to make routing decisions in the Banyan section of the network to route cells to the correct output port. This is summarized as follows: (z)xp -- (y,z)xp -- 1-stage network 3-stage network
Hence, the (3) x 1 network shown in Figure 20 refers to a single switch stage, and three routing bits are required to select from one of the eight output port groupings. (Recall that the QSE has 32 output ports that can be configured in groups of 1, 2, 4, 8, 16, or 32. In Figure 20, they are configured in groups of four. The input and output buffers provided by the QRT have four input ports and four output ports to the switch fabric, and are logically broken into the input half of the QRT (IRT) and output half of the QRT (ORT) for convenience.
x4 622 Mbps UTOPIA IRT x4 QSE
x4
x4
ORT
622 Mbps UTOPIA
Figure 20. (3) x 1 - 5 Gbps System
The (5) x 4 network shown in Figure 21 is an example of a network with four parallel planes. It demonstrates the flexibility allowed because the QRT has four input and output ports. In this case, randomization is performed in the IRT.
622 Mbps UTOPIA
x1 IRT x4 622 Mbps UTOPIA
QSE x1 Randomizer
x4
ORT
Figure 21. (5) x 4 - 20 Gbps System
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Issue 3
In Figure 22, the first stage of QSEs is configured to provide the required randomization, and the next two switch stages route the cells to the final port destination. The second QSE stage needs only to make an "up" or "down" decision requiring a single routing bit, while the third QSE stage needs to select between eight QRTs, requiring three routing bits.
622 Mbps UTOPIA
x4 IRT QSE
x16
x 16
x4
QSE
QSE
x4
x4 ORT 622 Mbps UTOPIA
QSE x 16
QSE x 16
QSE
Randomizer
Figure 22. (1,3) x 1 - 10 Gbps System
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PMC-980616 2.8.3 Speedup Factor (SF)
Issue 3
If the traffic pattern presented to a particular Banyan network results in many internal collision, a shuffling pattern exists that has been proven to result in few internal collisions. Although a purely random reshuffling results in good behavior, we can lower-bound network performance by using randomization along with the Evil Twin Switching algorithm as shown in Figure 23. This algorithm is as follows: randomly choose a configuration, route data, choose the dual or Evil Twin Switching configuration, route data, and repeat. This algorithm minimizes the number of internal collisions. In 3-stage networks, the first stage of the QSEs provide this functionality.
MNACK Randomly Choose Configuration Send Data Choose the Dual or Evil Twin Switching Configuration Send Data Input Buffers
ONACK
Local Arbiters
Intelligent Configuration Algorithm and Randomizer
Banyan
Output Buffers
Figure 23. Randomizer (with Evil Twin Switching Algorithm)
Even with a perfect crossbar for a network, there are still output collisions, and despite the Evil Twin Switching algorithm, there are still internal collisions (albeit fewer). Thus, multiple routing attempts must be made per cell to yield full throughput. This can be accomplished by running the switch fabric at a faster clock rate than the buffering logic.
Local Arbiters
Input Buffers
Output Buffers
Figure 24. Network Needs to be Run Faster than the Line Rate
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PMC-980616
Issue 3
The chance for internal collisions increases as the network load increases, and the exact behavior varies with network topology. An example of this behavior is shown in Figure 25 and the SF is inferred from the limiting case where the network is fully loaded.
Network Topology 1
PA = Probability of cell acceptance
PA
Limiting case, where the Load = 1, SF = 1/PA
0 Load
1
Figure 25. Definition of the Speedup Factor
Given this notion of SF, "how much faster is fast enough?" Theoretical models and simulations can answer that question. Given that the switch fabric can be run at a certain clock rate relative to the buffering logic, we can know which networks to choose to prevent the network from becoming a bottleneck.
2.0
Fabric Rate Speedup Factor (SF)
1.0 622 Mbps Network Size 160 Gbps
Figure 26. How to Use the SF to Select Favorable Networks
Table 2, Table 3 show all of the 1-, 3-stage network topologies requiring an SF of less than 1.6, which is the maximum speedup allowed by the actual implementation.
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PMC-980616
Issue 3
Table 2. Speedup Factor (1-Stage Networks) Network (3) x 1 (4) x 2 (5) x 4 5 10 20 Size (Gbps) Speedup Factor (SF) 1.22 1.36 1.57 1 2 4 Number of QSEs
Table 3. Speedup Factor (3-Stage Networks) Network (1,3) x 1 (1,4) x 2 (2,3) x 1 (2,4) x 2 (3,3) x 1 (3,4) x 2 (4,3) x 1 10 20 20 40 40 80 80 Size (Gbps) Speedup Factor (SF) 1.28 1.41 1.32 1.46 1.39 1.53 1.49 6 12 12 24 24 48 48 Number of QSEs
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3
EXTERNAL PORT DESCRIPTIONS
Switch Fabric Port and Interface Description
3.1
Each port is a 6-bit interface consisting of: * * * a nibble-wide data interface (SE_D_IN and SE_D_OUT), an SOC signal (SE_SOC_IN and SE_SOC_OUT), and a backpressure/data acknowledge signal (BP_ACK_IN and BP_ACK_OUT). SE_SOC Encodings
3.1.1
The SE_SOC encodings (SE_SOC_IN(31:0), SE_SOC_OUT(7:0)) provide guaranteed transitions and SOC encodings. The SE_SOC signals carry a repeating four "0s" and four "1s" pattern to guarantee transitions required by the phase aligner. The SOC signal on data lines associated with an SE_SOC line is indicated by a break in this repeating pattern. The SOC is a single "1" followed by five "0s". Figure 27 shows the guaranteed transitions. Figure 28 provides an expanded view of the signal transitions and the first nibble after the SOC pulse (nibble #0) corresponds to nibble "0" in Table 5 on page 40.
SE_CLK SE_SOC Four 1s Four 0s Five 0s
Start Of Cell Pulse
Four 1s
Four 0s
Four 1s
Four 0s
Figure 27. SE_SOC Encodings
Tsesu Magnified SE_CLK SE_DATA Magnified SE_SOC Four 1s
Tseho
Tsesu
#115. #116 #117 #0 Four 0s One
#1 Five 0s Four 1s
Start Of Cell Pulse
Figure 28. Expanded SE_SOC Encodings
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PMC-980616 3.1.2 Data Cell Format
Issue 3
The regular cell format is shown in Table 5.
Table 5. Regular Cell Format Symbol PRES(1:0), MC, SP Definition Pres = 10b: Cell present. 01b: Cell not present (See Table 6 on page 41). 00b: Cell assumed to be not present (failure). 11b: Cell assumed to be not present (failure). MC = 1b: Multicast Cell. SP Spare bit. SP(1:0) Spare bits. Priority = 11b: High-priority cell. 10b: Medium-priority cell. 01b: Low-priority cell. 00b: Undefined. Cell discarded by QSE. Comment The spare bit is not interpreted or used by the QSE.
Nibble
0
1
SP(1:0), PRIORITY(1:0)
Priority for the switching fabric. The QRT should be configured never to generate priority 00b cells, since they are discarded by the QSE. The spare bits are not interpreted or used by the QSE.
2
TAG_0
Routing tag 0 or MULTICAST_GROUP_INDEX(15:12). Refer to section 9.3.3 "MULTICAST_GROUP_INDEX_REGISTER" on page 96. Routing tag 1 or MULTICAST_GROUP_INDEX(11:8). Refer to section 9.3.3 "MULTICAST_GROUP_INDEX_REGISTER" on page 96. Routing tag 2 or MULTICAST_GROUP_INDEX(7:4). Refer to section 9.3.3 "MULTICAST_GROUP_INDEX_REGISTER" on page 96. Routing tag 3 or MULTICAST_GROUP_INDEX(3:0). Refer to section 9.3.3 "MULTICAST_GROUP_INDEX_REGISTER" on page 96. Routing tag 4 or MULTICAST_GROUP_INDEX(23:20). Currently, QSE supports only 256K multicast group vectors, i.e. it only uses multicast group index(17:0). Therefore, bits 23:20 are ignored. Currently, QSE supports only 256K multicast group vectors, i.e. it only uses multicast group index(17:0). Therefore, bits (19:18) are ignored. Interpretation of TAG_5:0 depends on whether or not the cell is a multicast cell.
3
TAG_1
4
TAG_2
5
TAG_3
6
TAG_4
7
TAG_5
Routing tag 5 or MULTICAST_GROUP_INDEX(19:16). Refer to section 9.3.8 "MULTICAST_GROUP_INDEX_MSB" on page 98. Routing tag 6.
8
TAG_6
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PMC-980616
Issue 3
Table 5. Regular Cell Format (Continued) Symbol Definition Routing tag 7. Interpreted as OUTCHAN(15:12) by a QRT.
Nibble
Comment
9
TAG_7 OUTCHAN_3 SP(1:0), MB, PARITY
10 11
Not used by the QSE.
SP(1:0) Spare bits. MB Mark bit: Cells that are present and have this bit set are counted by the INPUT_MARKED_CELL_COUNT (refer to section 9.3.11 "INPUT_MARKED_CELLS_COUNT" on page 99) and OUTPUT_MARKED_CELL_COUNT (refer to section 9.3.12 "OUTPUT_MARKED_CELLS_COUNT" on page 99) counters. P Should be odd parity over nibbles 0 to 11. Interpreted as OUTCHAN(11:8) by a QRT. Interpreted as OUTCHAN(7:4) by a QRT. Interpreted as OUTCHAN(3:0) by a QRT. Interpreted as Virtual Channel Identifier (VCI)(15:12) by a QRT. Interpreted as VCI(11:8) by a QRT. Interpreted as VCI(7:4) by a QRT. Interpreted as VCI(3:0) by a QRT. Interpreted as the Payload Type Indicator (PTI) and Cell Loss Priority (CLP) fields from the cell by a PM73487A. Interpreted as SEQ(7:4) by a QRT. Interpreted as SEQ(3:0) by a QRT. Interpreted as 48 bytes of ATM cell payload by a QRT. Not used by the QSE. Not used by the QSE. Not used by the QSE. Not used by the QSE. Not used by the QSE. Not used by the QSE. Not used by the QSE. Not used by the QSE. Not used by the QSE. Not used by the QSE. Not used by the QSE.
12 13 14 15
OUTCHAN_2 OUTCHAN_1 OUTCHAN_0 VCI_3 VCI_2 VCI_1 VCI_0 PTI(2:0)/CLP SEQ_1 SEQ_0 Payload
16 17 18 19 20 21
22-117
The idle cell format is shown in Table 6. The idle cell format is chosen to make the interface robust to both stuck-at faults, as well as bridging faults on the data lines.
Table 6. PM73488 Mode Idle Cell Format Symbol Pres(3:0) IDLE_0 IDLE_1 Definition Pres = 0100b: Cell not present. IDLE_0 = 0000b: All 0. IDLE_1 = 1000b: Marching 1 pattern, which protects against bridging faults. Comment
Nibble
0
1
2
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Issue 3
Table 6. PM73488 Mode Idle Cell Format (Continued) Symbol IDLE_2 IDLE_3 IDLE_4 IDLE_5 IDLE_6 Reserved Unused Definition IDLE_2 = 0100b: Marching 1 pattern, which protects against bridging faults. IDLE_3 = 0010b: Marching 1 pattern, which protects against bridging faults. IDLE_4 = 0001b: Marching 1 pattern, which protects against bridging faults. IDLE_5 = 0000b: IDLE_6 = 0000b. (QSE currently outputs 0000b.) (QSE currently outputs 0000b.) Comment
Nibble
3
4 5 6 7
8-15
16-117
3.1.3
BP_ACK Encodings
The BP_ACK encodings (BP_ACK_IN and BP_ACK_OUT) guarantee transitions, and BP and ACK encodings are shown in Figure 29. The BP_ACK signal is used to signal backpressure/cell acknowledgment to the previous stage. To ensure the transitions required by the phase aligner, this line carries a repeating four "0s" and four "1s" pattern. The actual information is transferred by a break in this pattern (shown by BP_ACK signaling in Figure 29). The pattern break is identified by a bit inversion (Inversion 1) on the line, followed by a mode, and two data bits, followed by a second inversion (Inversion2) of the expected bit, if the previous pattern had continued. This is followed by the last two bits. After these information bits, the repeating pattern restarts with four "0s".
SE_CLK BP_ACK Base Pattern BP_ACK Signaling
Data3 Mode Inversion 1 Data2 Data1 Inversion 2 Data0
Four 1s
Four 0s
Four 1s Four 0s
Four 0s Four 1s
Figure 29. BP_ACK Encodings
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PMC-980616 The information bits encoding is described in Table 7.
Issue 3
Table 7. Information Bit Encoding Data 3 1 = Backpressure on high-priority multicast cell. Data 2 1 = Backpressure on medium-priority multicast cell. Data 1 1 = Backpressure on low-priority multicast cell. Data 0 0 Description Backpressure information. This signal is present each cell time regardless of whether a cell was transmitted or not (on that link). This signal is withheld if any problem is detected on the input port. Unassigned. Signals MNACK. Signals ONACK. Signals ACK.
Mode
0
1 1 1 1
0 0 1 1
0 1 0 1
0 0 0 0
0 0 0 0
3.2
Data Acknowledge
The data acknowledge signals (BP_ACK_IN and BP_ACK_OUT) are used to indicate if, at the current cell time, a cell was successfully transmitted or not. Data acknowledge is a single line per port that returns from a cell's destination in the reverse direction from the data flow. If the cell is being blocked by the switch, this information is generated directly by the QSE. If the cell is not being blocked by the switch, this information is forwarded from the next switch stage. The data acknowledge signal provides the following information to the QRT: * * * * The cell was successfully received by the QRT at the cell destination (ACK). The cell was not accepted by the QRT at the cell destination (does not happen by design in the PM73487). The cell was blocked by the switch at the output of the switch fabric (refer to section 9.3.30 "ACK_PAYLOAD" on page 109). The cell was blocked internal to the switch fabric (refer to section 9.3.30 "ACK_PAYLOAD" on page 109). The cell was detected as a parity error cell by a QSE (refer to section 9.3.30 "ACK_PAYLOAD" on page 109). The cell was headed to a gang of which all ports are dead (refer to section 9.3.31 "GANG_DEAD_ACK_PAYLOAD" on page 110).
*
*
Thus, direct information is provided to the QRT on a per-cell basis and on a per-VC basis. The QSE behavior to support the above scenario is as follows: * If the cell was a parity errored cell, and the QSE is configured to check parity in the CHIP_MODE register (refer to the field labeled "PARITY_CHECK" on page 95), then the parity acknowledge in the ACK_PAYLOAD register is sent (the default is ONACK). If the cell is dropped due to congestion at an output of the QSE, then Ack Payload for cells dropped due to congestion in the ACK_PAYLOAD register is sent (bits3:0). Refer to bits 3:0 in section 9.3.31 "GANG_DEAD_ACK_PAYLOAD" on page 110.
*
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Issue 3
If the cell was blocked at an output of the QSE because the entire gang is disabled (the default is ACK), then the cell is to be cleared when all ports to a QRT are known to be unavailable. If the cell was successfully routed through the QSE, the return path is set up to route the data-acknowledge signal back from the next switch stage.
*
For multicast traffic, the BP_ACK_IN and BP_ACK_OUT signals also serve as a backpressure signal, indicating at each cell time, the multicast cell priority the QSE can accept on the following cell time on a given port. 3.3 Microprocessor Interface
The QSE has a non-multiplexed, asynchronous, general-purpose microprocessor interface (PIF) through which the internal registers can be accessed. The external SSRAM is also indirectly accessed through this same interface. 3.4 Multicast SRAM Interface
The QSE supports 128 internal multicast groups, and is expandable up to 256K through an external SSRAM. 3.5 Clocks and Timing Signals
The QSE is driven from a single clock source up to a maximum clock rate of 66 MHz. To indicate the SOC, there is one SE_SOC_IN signal per input port. There is one SE_SOC_OUT signal per group of four outputs. Cells must arrive at the input ports within an eight clock-cycle window. A CELL_START is used as a reference for an internal cell start signal to determine the eight clock-cycle window in which the SOC signal on the SE_SOC_IN lines are valid. The internal cell start signal delay from the external CELL_START signal is programmed in the CELL_START_OFFSET (refer to section 9.3.28 "CELL_START_OFFSET" on page 109). CTRL_IN
3.6
CTRL_IN is a one bit input port. Its function depends on the value of the "ENABLE_STAT_PINS" (bit 7) bit in the CHIP_MODE register. When this bit is "0", CTRL_IN directly sets the value of the internal "No Data Out" control bit. What this internal bit does is explained later. When this bit is "1", CTRL_IN expects a data packet which sets the value of both, the internal "/No Data Out" and the "/No Data In" registers. The format for the data packet is described below:
Data on this line has to be clocked out by its source at one-eighth the QSE clock rate. CTRL_IN is normally "0". A valid data packet starts with a "0" -> "1" transition on the line (implying that the first "bit" of the data packet is "1"). A valid data packet starts with "100b" followed by 2 control bits and 6 bits which are ignored. If the first 3 bits of a data packet are not "100b", the data packet is ignored (i.e. the next 8 bits are ignored). Data packets may not arrive back to back. At least 4 zero bits must be present between any two data packets.
A valid data packet is therefore: "100b0b1XXXXXX b". b0 is the desired value of "/No Data In" and b1 is the desired value of "/No Data Out". If the internal "/No Data In" bit is asserted the QSE will continously apply back pressure on all inputs and all priorities. If the internal "/No Data Out" bit is asserted the QSE will behave as if all its outputs are receiving backpressure on all priorities.
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PMC-980616 3.7 STAT_OUT
Issue 3
This is a bidirectional port whose function depends on the value of the "ENABLE_STAT_PINS" (bit 7) bit in the CHIP_MODE register. When this bit is "0", STAT_OUT is configured as an input port and directly sets the value of the "No Data In" internal register (see CTRL_IN description above for what this internal register does). When this bit (ENABLE_STAT_PINS) is "1", STAT_OUT is configured as an output and periodically outputs an information packet which indicates whether the internal multicast buffers are empty.
STAT_OUT is normally "0" and the information packet generated on the STAT_OUT pin is 5 bits long and is clocked out using the QSE clock. The pattern starts with a "1" and the 5 bits are "10b0b1b2" including the "1" that starts it all. If b0b1b2 is "000", then it means that all the multicast buffers are empty. If b0b1b2 is any other three-bit value, then it means that the multicast buffers are not empty. Note that this packet represents the instantaneous status of the multicast buffers. Therefore, if a multicast cell is entering or exiting the chip at just about the time the packet is being output, then the information in the packet must be interpreted with caution. However such delicate race conditions are not a problem in practice. (See "Fabric Switch-Over" on page 45.) 3.8 Fabric Switch-Over
The reason /NO_DATA_IN, /NO_DATA_OUT and STAT_OUT exist is to support hitless fabric switch-over. This means that we wish to detour traffic to a back-up fabric and take the current fabric down for repairs, all without losing a single cell. This can be accomplished in several different ways. We suggest a possible scheme below. Our scheme only uses the /NO_DATA_IN and STAT_OUT features. Other schemes may also use the /NO_DATA_OUT feature. There are two fabrics, A and B. Each fabric has two kinds of inputs: data_in and bp_ack_in. Assume that these inputs are duplicated to both fabrics. Each fabric also has two kinds of outputs: data_out and bpack_out. Assume that there are muxes that can choose outputs either from fabric A or from fabric B. At any point in time, all muxes must select A, or all muxes must select B, i.e. all muxes must switch in lock-step. Initially, we are using fabric A, and B is the back-up. Thus all muxes are set to choose A. At the end of the process, we want to be using fabric B, with A being the back-up. During the process, no cell must get lost, and there should be no ordering violations. * Assert /NO_DATA_IN on both A and B. For unicast, the result is that both A and B will reject cells and return nacks. For multicast, the result is that both A and B will assert full back-pressure. Of course, only the nacks and back-pressure from A will reach the ingress QRTs, because the muxes are set to choose A. Effectively, the QRT will not be able to deliver even a single cell. All unicast cells will be attempted, but they will bounce back with nacks. Multicast cells can't even be attempted because of full back-pressure. Wait for STAT_OUT to go to "000" on all QSEs on both fabrics. This indicates that all multicast cells that were in transit in the fabrics have drained out. Of course, only the cells from A will reach the egress QRTs, because the muxes are set to choose A. At a cell time boundary, switch all muxes to choose B. Now deassert /NO_DATA_IN on both A and B. Cells will start flowing through B, and A can be taken down safely for maintenance/repair.
* *
* *
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PMC-980616 3.9 Cell Timing/Latency
Issue 3
The data latency through each QSE depends on the distribution mode. The maximum data latency is listed in Table 8.
Table 8. Data Latencies Aggregate Mode 1 2, 4, 8, 16, 32 Latency 13 clock cycles 10 clock cycles
The data acknowledge through each QSE is a maximum of five clock cycles.
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4
QSE FEATURE DESCRIPTIONS
Distribution Algorithm
4.1
The QSE has an algorithm that allows unicast cells to take advantage of multiple paths in multistage switch fabrics. This algorithm is run simultaneously by all QSEs in a system. Since the position (row and column) of each QSE is known (refer to section 9.3.26 "SWITCH_FABRIC_ROW" on page 107 and to section 9.3.27 "SWITCH_FABRIC_COLUMN" on page 108), and they all receive a synchronizing strobe (CELL_24_START), each QSE can determine exactly what the other QSEs are doing. This enables the QSEs to act globally to minimize cell congestion in the switch fabric. 4.2 Cell Start Offset Logic
Each QSE needs to be informed when the window occurs during which the SE_SOC_IN is valid for the input ports. Generally, since this window can vary from one QSE to another in the fabric, it is made software programmable by setting the CELL_START_OFFSET register (refer to section 9.3.28 "CELL_START_OFFSET" on page 109). The significance of this register is as follows: The QSE generates an internal signal called "Local CELL_START", which is simply a delayed version of external CELL_START input, where the delay is the number of clock cycles given in the CELL_START_OFFSET register. The valid window for accepting SE_SOC_IN is the 8-clock-cycle interval immediately preceding the pulse of local CELL_START signal. (For a detailed timing diagram, see "Relation Between External CELL_START and Local CELL_START" on page 47.) 4.2.1 Relation Between External CELL_START and Local CELL_START
Figure 30 shows the relationship between the external CELL_START signal and the local CELL_START signal, which is used internally by the QSE. The signal offset is programmable through the microprocessor interface (refer to section 9.3.28 "CELL_START_OFFSET" on page 109) to allow for easy system synchronization.
Clock Cycle Tseau SE_CLK External CELL_START
CST Low
CSTART Delay CST High Tesu
Delta Delta Local CELL_START Valid SOC Pulses 8 Clock Cycles SOC Pulses SOC Pulses Derived from the SE_SOC_IN Signals
Figure 30. QSE Cell-Level Timing
The QSE performs cut-through routing wherever possible and requires the SOC to be synchronized across all input ports. For greater flexibility, the QSE allows cells starting within a window of eight clock pulses to be considered valid. The end of the 8-clock-cycle window is also indicated by the local CELL_START signal.
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PMC-980616 4.2.2
Issue 3
Relation Between Local CELL_START and Data Out of the QSE
The QSE switch latency from the local CELL_START signal to the first nibble depends on the gang mode, as shown in Figure 31. The switch latency is 8 clocks from the local CELL_START signal for all unicast gang modes, except for unicast gang mode = 0, in which case the switch latency is 11 clocks..
SE_CLK
Local CELL_START End of 8 CLK Valid Window SOC Pulses Gang Mode not = 1 SE_D_OUT #115. #116. #117. #0 #1 #2 #3
SE_SOC_OUT Gang Mode = 1 SE_D_OUT(1) #115. #116. #117. #0
SE_SOC_OUT(1)
Figure 31. QSE Switch Latency
The CELL_24_START signal is used as a strobe to synchronize the internal state machines of all QSEs and QRTs in the system. When it occurs, the CELL_24_START signal must be coincident with the CELL_START signal and should occur every 4Nth cell time. (The signal is called CELL_24_START for legacy reasons that are no longer relevant.) 4.3 General Description of Phase Aligners
The phase aligners recover a clock from the data in the QSE-to-QSE, QRT-to-QSE, and QSE-to-QRT interfaces as shown in Figure 32 on page 49. The forward cell path consists of five signals, SE_D(3:0) and SE_SOC, while the backward path consists of one signal, BP_ACK. In the forward cell path, the phase aligners lock to the SE_SOC_IN signal that has guaranteed signal transitions. The recovered clock is then used to sample the other signals, SE_D_IN(3:0). In the backward path, the phase aligners lock to the BP_ACK_IN signal that has guaranteed signal transitions.
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QRT-to-QSE Interface
QSE-to-QRT Interface
QRT (IRT Portion) A QSE (Switching Matrix) QRT (IRT Portion) B QSE-to-QSE Interface QSE (Switching Matrix)
QRT (ORT Portion) A
QRT (ORT Portion) B
Forward Cell Flow Backward BP/ACK Flow
Figure 32. Basic Forward and Backward Data Path
4.4
Multicast Backpressure Control
As described in section 2.4.1 "Multicast Queue Engine" on page 28, the multicast queue engine computes multipriority backpressure (high, medium, or low) based on the following factors: * * Total buffer usage. Buffer usage on an individual port.
The buffer use constraints described therein guarantee against one port flooding the QSE and choking other ports (by the per-port buffer limits) or heavy traffic from cells of a lower priority level choking cells of higher priorities (by allowing buffers to be reserved for high- and medium-priority cells). The QSE is tolerant of the QRT and other QSEs on its input ignoring the backpressure it applies. Depending on the situation, cells that arrive in violation of recommended backpressure may be dropped or may be accepted and treated as normal cells. This is fault behavior since, during normal operation, neither the QSE nor the QRT will ever violate backpressure applied by a downstream QSE. 4.5 Multilevel Reset
When the RESET pin is asserted, the QSE is in total reset. Access is not permitted to any register; and all QSE-driven signals, except for RAM_CLK, are static at either 0 or 1.
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When the CHIP_HARDWARE_RESET bit in the CHIP_MODE register (refer to section 9.3.2 "CHIP_MODE" on page 95) is enabled, all registers can be read from and written to, but do not attempt to access the multicast port vectors in the multicast RAM. The rest of the device is in full reset.
When the CHIP_HARDWARE_RESET bit in the CHIP_MODE register (refer to section 9.3.2 "CHIP_MODE" on page 95) is disabled, but the SW_RESET bit in the CONTROL_REGISTER (refer to section 9.3.22 "CONTROL_REGISTER" on page 103) is enabled, the processor has fast access to the multicast RAM. This mode allows the multicast port vectors to be set up quickly at initialization. In normal device operation, the microprocessor has a single multicast RAM access every 118 clocks.
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5. FAULT SPECIFICATION
5. 1. Purpose The purpose of this chapter is to provide system designers with the high-level failure behavior of the system. It documents the algorithms used, as well as the QRT- and QSE-specific behaviors required. 5. 2. Basic Data and BP/ACK Flow The basic data path through the QRT and QSE is shown in Figure 33. In this example, data enters the switch through a UTOPIA interface at the IRT portion on the QRT and is queued in the IRT. Then, cells are played out to the switch fabric (which consists of one or more stages of QSEs), and finally enters the ORT portion of the QRT where it is queued. Cells are then played out of the switch through a UTOPIA interface. Failures within the switch fabric are looked for, excluding the UTOPIA interfaces.
QRT-to-QSE Interface
QSE-to-QRT Interface
QRT (IRT Portion) a
b
A QSE f (Switching c Matrix) e
QRT g h (ORT Portion) A
c d
e
d
QRT (IRT Portion) a
f
d
QSE f (Switching c Matrix) e
c d
e
f
QRT (ORT Portion)
b
B QSE-to-QSE Interface
g h
B
Forward Cell Path Backward BP/ACK Path
Figure 33. Basic Data Path (SE_D_OUT/IN and SE_SOC_OUT/IN in Forward Path, BP_ACK_OUT/IN in Backward Path)
It is important to decide at the beginning what level of fault diagnosis, recovery, and additional functionality is desired. The goal is to be robust to: * * * Any stuck-at fault, Any bridging fault within a port, and Possible card removal.
In particular, the system should not be totally disabled by any of the above, although it may operate at a reduced performance. In addition, any of the previous failures should be locatable. The system will not necessarily be robust to:
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PMC-980616 * * * All dribbling errors, Any bridging fault between ports, and Complex partial failures.
Issue 3
As much as possible, the following secondary goals will be taken into account in the algorithms implemented. * * * * * * * Quick and responsive in failure detection, Localize the problem, and minimize the effect of the problem, Avoid throughput collapse, Identify and locate the problem, Possibly do strong manufacturing test, On line diagnostics, and Automatically detect when a failure resolves itself.
5. 3. Fault Detection Mechanisms Several mechanisms are built into the QSE and the QRT to facilitate online detection and location of faults within a system. These involve: * * * * * Special coding and guaranteed transitions on the BP_ACK line. If this is not detected, the condition is flagged, and no data is sent out on the port. Special coding and guaranteed transitions on the SE_SOC line. If this is not detected, the port is flagged as failed, and all data from the port is discarded. Cell present being marked by two bits, Nibble 0 is 10xx for cell present or 01xx for cell absent (11xx and 00xx are considered errors, the port is flagged as failed, and all data from the port is discarded). Idle cell is coded by five nibbles, (01xx, 0000,1000, 0100, 0010, 0001). This pattern verifies no line has a stuck-at or bridging fault. Closed loop port behavior ensures no data is sent to a bad port. If a port is flagged as failed, then no BP signal is sent back on the BP_ACK line. This in turn will be detected by the transmitting QSE, and will be flagged. In addition, no data will be sent to that port while the condition exists. Nibbles 1 through 12 of the cell header are parity protected. For unicast data, in the QRT, a parity errored cell is dropped, but an ACK is still issued. In the QSE, an ONACK is issued for parity errored cells. This results in the unicast ONACKed cell being retransmitted if the parity error did not occur in the last stage. For multicast data, parity errored cells are dropped by both the QRT and QSE. Marked cell count. All input and output ports have a 4-bit cell counter. Any cell that goes by with a marked cell count bit set increments this count. (Note that unicast traffic has to be ACKed to increment the count.) Modulo 16 arithmetic can be performed on these counts to determine if there was any unexpected cell loss or generation. Whenever a port is tagged dead due to BP_ACK failure, there needs to be two consecutive good instances to make the port alive again.
*
*
*
5. 4. Interface Behavior In Figure 33 on page 51, the various interfaces of interest are labeled a, b, c, d, e, f, g, and h respectively.
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PMC-980616 5. 5. IRT-to-Switch Fabric Interface
Issue 3
An IRT interface consists of a and b in Figure 33 on page 51. Where a refers to each of the four SE_SOC_OUT and SE_D_OUT(3:0) data ports, and b refers to the corresponding BP_ACK_IN signals in the QRT. The failure conditions detected by the IRT on b, and the actions taken are summarized in Table 9.
Table 9. Failure Conditions, IRT-to Switch Fabric Interface Fault Detected on b Action Taken Idle cells sent out on data interface a. Internally to the IRT, cells that would have gone out are MNACKed, and no multicast cells are generated for the port. BP_ACK_FAIL signaled to the microprocessor. Idle cells sent out on data interface a. Internally to the IRT, cells that would have gone out are MNACKed, and no multicast cells are generated for the port. BP_REMOTE_FAIL signaled to the microprocessor. Cell transmitted treated as sent. ACK_LIVE_FAIL signaled to the microprocessor. Comment Port treated as dead. Problem is most likely with the BP_ACK_IN line.
Cannot lock to special coding and guaranteed transitions on BP_ACK_IN.
No BP received on BP_ACK_IN line.
Port treated as dead. Problem is with the forward data flow, and the QSE is signaling this back to the IRT.
No ACK, MNACK, or ONACK received, although unicast cell sent out.
5. 6. QSE Interface, Receive Data Direction
A QSE Receive interface consists of c and d in Figure 33 on page 51. Where c refers to each of the four SE_SOC_IN and SE_D_IN(3:0) data ports, and d refers to the corresponding BP_ACK_OUT signals in the QSE.
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The failure conditions detected by the ORT on c, and the actions taken are summarized in Table 10.
Table 10. Failure Conditions, QSE Receive Interface Fault Detected on c Action Taken No BP sent out on d. All data discarded. SE_INPUT_PORT_FAIL signaled to the microprocessor. No BP sent out on d. All data discarded. SE_INPUT_PORT_FAIL signaled to the microprocessor. Comment Withholding BP on d signals to the previous stage that the port should not be used. Most likely due to unconnected input lines that are pulled up or down. Withholding BP on d signals to the previous stage that the port should not be used. Withholding BP on d signals to the previous stage that the port should not be used. QSE does not necessarily have time to drop cell by the time it has detected a parity error.
Cannot lock to special coding and guaranteed transitions on SE_SOC_IN. Invalid cell present coding on SE_D_IN(3:0).
Bad idle cell coding on SE_D_IN(3:0). Parity fail.
No BP sent out on d. All data discarded. SE_INPUT_PORT_FAIL signaled to the microprocessor. ONACK sent out on d for unicast data. Multicast data dropped. PARITY_FAIL signaled to the microprocessor.
5. 7. QSE Interface, Transmit Data Direction A QSE Transmit interface consists of e and f in Figure 33 on page 51. Where e refers to each of the 32 SE_SOC_OUT and SE_D_OUT(3:0) data ports, and f refers to the corresponding BP_ACK_IN signals in the QSE.
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The failure conditions detected by the QSE on f, and the actions taken are summarized in Table 11.
Table 11. Failure Conditions, QSE Transmit Interface Fault Detected on f Action Taken Idle cells sent out on data interface e. Data routed around port if possible. Multicast data is dropped if all possible port choices are dead or off. Unicast data is optionally dropped if all possible port choices are dead or off. BP_ACK_FAIL signaled to the microprocessor. Idle cells sent out on data interface e. Data routed around port if possible. Multicast data is dropped if all possible port choices are dead or off. Unicast data is optionally dropped if all possible port choices are dead or off. BP_REMOTE_FAIL signaled to the microprocessor. No action taken. Comment Port treated as dead. Problem is most likely with the BP_ACK line.
Cannot lock to special coding and guaranteed transitions on BP_ACK_IN.
No BP received on BP_ACK_IN line.
Port treated as dead. Problem is with the forward data flow.
No ACK, MNACK, or ONACK received on BP_ACK_IN line.
This contingency is not monitored in the QSE.
5. 8. Switch Fabric-to-ORT Interface An ORT interface consists of g and h in Figure 33 on page 51. Where g refers to each of the four SE_SOC_IN and SE_D_IN(3:0) data ports, and h refers to the corresponding BP_ACK_OUT signals in the QRT.
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
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PMC-980616
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The failure conditions detected by the ORT on g, and the actions taken are summarized in Table 12.
Table 12. Failure Conditions, Switch Fabric-to-ORT Interface Fault Detected on g Action Taken No BP sent out on h. All data discarded. SE_INPUT_PORT_FAIL signaled to the microprocessor. No BP sent out on h. All data discarded. SE_INPUT_PORT_FAIL signaled to the microprocessor. Comment Withholding BP on h signals to the previous stage that the port should not be used. Most likely due to unconnected input lines that are pulled up or down. Withholding BP on h signals to the previous stage that the port should not be used. Withholding BP on h signals to the previous stage that the port should not be used. ACK already sent by the time the QRT has detected a parity error. Note that in this case we have ACKed a cell that was dropped.
Cannot lock to special coding and guaranteed transitions on SE_SOC_IN. Invalid cell present coding on SE_D_IN(3:0).
Bad idle cell coding on SE_D_IN(3:0). Parity fail.
No BP sent out on h. All data discarded. SE_INPUT_PORT_FAIL signaled to the microprocessor. ACK sent out on h. Parity errored cell dropped. TX_PARITY_FAIL signaled to the microprocessor.
5. 9. Types of Failures and Their Manifestation Possible faults, the effects and how they affect the network are shown in Table 13.
Table 13. Faults Fault Manifestation Effect on Network
Wire Connection Data line from SE_D(3:0) stuck at 0 or 1. Invalid idle cell, with some 10/01 fail and parity error. Loss of lock on special coding on SE_SOC_IN. Loss of lock on special coding on BP_ACK_IN. Invalid idle cell, with some 10/01 fail and parity error. Port shut down on receipt of first bad idle cell until condition is fixed, as port failure is sent back to source of data by the lack of BP indication. Port shut down until condition is fixed, as port failure is sent back to source of data by the lack of BP indication. Port shut down until the condition is fixed. Port shut down on receipt of first bad idle cell until condition is fixed, as port failure is sent back to source of data by the lack of BP indication.
SE_SOC line stuck at 0 or 1.
BP_ACK line stuck at 0 or 1.
Bridging fault within a port.
QRT and QSE Port Failures No SE_SOC_OUT generation. Loss of lock on special coding on SE_SOC_IN. Port shut down until condition is fixed, as port failure is sent back to source of data by the lack of BP indication.
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Table 13. Faults Fault Manifestation 10/01 Fail, or parity error, invalid idle cell. Loss of lock on special coding on BP_ACK_IN.
Effect on Network Port shut down on receipt of first bad idle cell until condition is fixed, as port failure is sent back to source of data by the lack of BP indication. Port shut down until the condition is fixed.
No/Invalid data generated.
No BP_ACK_OUT generation.
QSE Chip Failures Multicast handling. MC Cell pool buffer. Cell loss or generation. Parity error in header or cell. Parity error in header and cell. Cell gets out on wrong port, cell duplicated, cell lost. Cell lost. Detection possible using marked cell count. Only detection in header, not in payload. Parity error. Cell to wrong port may be noticed by receiving QRT, if that VC is not active. cell duplication and cell loss detection possible using marked cell count. Detection possible using marked cell count.
Partial cell buffers.
Multicast and Unicast selection networks.
Arbiter.
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6
SIGNAL DESCRIPTIONS
6.1 Package Diagram A 596-pin Enhanced Plastic Ball Grid Array (EPBGA), shown in Figure 34 (part 1 and part 2), is used for the QSE.The package measurements are shown in millimeters.
40.00 0.20
Measurements are shown in millimeters. Not drawn to scale.
30.00 MAX.
QSE
PM73488-PI
L2A0962 L_______B Lyyww
1.14 0.125
2.98 Max.
0.86 0.15
NOTES: 1. "L2A0962" is the LSI part number. 2. "L_____B" is the wafer batch code. 3. "Lyyww" is the assembly date code. 4. Dimensions are for reference. 5. Controlling dimension: millimeter. 6. // = Parallelism tolerance.
Figure 34.
596-Ball Enhanced Plastic BGA Physical Dimensions Diagram (Top view)
// 0.25 0.10
0.60 0.1
C C
30.00 MAX.
40.00 0.20
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Measurements are shown in millimeters. Not drawn to scale. 40.00 0.20 36.83 1.27 0.75 0.15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 40.00 0.20 36.83
1.27
AK AJ AH AG AF AE AD AC AB AA Y W V
UTRPNML
KJ
HGF
EDCB
A
S
0.30 S C A NOTES: 0.10 S C 1. Controlling dimension: millimeter. 2. PCB material: high temperature glass/epoxy resin cloth (that is, driclad, MCL-679, or equivalent). Solder resist: photoimagable (that is, vacrel 8130, DSR3241, PSR4000, or equivalent). 3. If you need a measurement not shown in this figure, contact PMC.
B
S
Figure 35. 596-Ball Enhanced Plastic BGA Physical Dimensions Diagram (Bottom view)
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PMC-980616 6.2 Signal Locations (Signal Name to Ball)
Issue 3
Table 14. Signal Locations (Signal Name to Ball) Signal Name
BP_ACK_IN(0) BP_ACK_IN(1) BP_ACK_IN(2) BP_ACK_IN(3) BP_ACK_IN(4) BP_ACK_IN(5) BP_ACK_IN(6) BP_ACK_IN(7) BP_ACK_IN(8) BP_ACK_IN(9) BP_ACK_IN(10) BP_ACK_IN(11) BP_ACK_IN(12) BP_ACK_IN(13) BP_ACK_IN(14) BP_ACK_IN(15) BP_ACK_IN(16) BP_ACK_IN(17) BP_ACK_IN(18) BP_ACK_IN(19) BP_ACK_IN(20) BP_ACK_IN(21) BP_ACK_IN(22) BP_ACK_IN(23) BP_ACK_IN(24) BP_ACK_IN(25) BP_ACK_IN(26) BP_ACK_IN(27) BP_ACK_IN(28) BP_ACK_IN(29) BP_ACK_IN(30) BP_ACK_IN(31) BP_ACK_OUT(0) BP_ACK_OUT(1) BP_ACK_OUT(2)
Ball
L29 K30 G30 N27 J29 M28 H30 L27 M26 H29 K28 F30 N25 M25 J28 L26 D30 G29 J27 K27 K26 J26 H28 D29 C30 F28 E29 K25 C29 J25 D28 H26 AB5 AF2 AA6
Signal Name
SE_D_IN11(1) SE_D_IN11(2) SE_D_IN11(3) SE_D_IN12(0) SE_D_IN12(1) SE_D_IN12(2) SE_D_IN12(3) SE_D_IN13(0) SE_D_IN13(1) SE_D_IN13(2) SE_D_IN13(3) SE_D_IN14(0) SE_D_IN14(1) SE_D_IN14(2) SE_D_IN14(3) SE_D_IN15(0) SE_D_IN15(1) SE_D_IN15(2) SE_D_IN15(3) SE_D_IN16(0) SE_D_IN16(1) SE_D_IN16(2) SE_D_IN16(3) SE_D_IN17(0) SE_D_IN17(1) SE_D_IN17(2) SE_D_IN17(3) SE_D_IN18(0) SE_D_IN18(1) SE_D_IN18(2) SE_D_IN18(3) SE_D_IN19(0) SE_D_IN19(1) SE_D_IN19(2) SE_D_IN19(3)
Ball
B7 C9 D10 A4 C8 D9 A3 B5 F10 B4 F9 E8 B3 D7 F7 D6 E7 E6 D5 F3 C1 D2 H3 K5 K4 J4 G2 L5 J3 M6 N6 K3 H2 M5 L4
Signal Name
SE_D_OUT16(2) SE_D_OUT16(3) SE_D_OUT17(0) SE_D_OUT17(1) SE_D_OUT17(2) SE_D_OUT17(3) SE_D_OUT18(0) SE_D_OUT18(1) SE_D_OUT18(2) SE_D_OUT18(3) SE_D_OUT19(0) SE_D_OUT19(1) SE_D_OUT19(2) SE_D_OUT19(3) SE_D_OUT20(0) SE_D_OUT20(1) SE_D_OUT20(2) SE_D_OUT20(3) SE_D_OUT21(0) SE_D_OUT21(1) SE_D_OUT21(2) SE_D_OUT21(3) SE_D_OUT22(0) SE_D_OUT22(1) SE_D_OUT22(2) SE_D_OUT22(3) SE_D_OUT23(0) SE_D_OUT23(1) SE_D_OUT23(2) SE_D_OUT23(3) SE_D_OUT24(0) SE_D_OUT24(1) SE_D_OUT24(2) SE_D_OUT24(3) SE_D_OUT25(0)
Ball
AE24 AG26 AJ28 AE22 AH27 AF23 AK28 AH25 AJ26 AE21 AF21 AF22 AH23 AJ27 AF20 AK27 AJ24 AG22 AK25 AE18 AE19 AH22 AG20 AF19 AJ23 AH21 AG18 AJ22 AH19 AK23 AE17 AH18 AJ20 AK21 AK20
Signal Name
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Ball
R3 T3 V1 AA2 W4 AF1 AD3 AJ2 AG4 AE6 AF3 AH5 AK5 AH7 AJ10 AG12 AK13 AH15 AH16 AK18 AJ21 AG19 AK26 AH24 AH26 AJ29 AG27 AE25 AF28 AF30 AD28 AA29 W27 V30 T28
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PMC-980616
Issue 3
Table 14. Signal Locations (Signal Name to Ball) (Continued) Signal Name
BP_ACK_OUT(3) BP_ACK_OUT(4) BP_ACK_OUT(5) BP_ACK_OUT(6) BP_ACK_OUT(7) BP_ACK_OUT(8) BP_ACK_OUT(9) BP_ACK_OUT(10) BP_ACK_OUT(11) BP_ACK_OUT(12) BP_ACK_OUT(13) BP_ACK_OUT(14) BP_ACK_OUT(15) BP_ACK_OUT(16) BP_ACK_OUT(17) BP_ACK_OUT(18) BP_ACK_OUT(19) BP_ACK_OUT(20) BP_ACK_OUT(21) BP_ACK_OUT(22) BP_ACK_OUT(23) BP_ACK_OUT(24) BP_ACK_OUT(25) BP_ACK_OUT(26) BP_ACK_OUT(27) BP_ACK_OUT(28) BP_ACK_OUT(29) BP_ACK_OUT(30) BP_ACK_OUT(31) CELL_24_START CELL_START RAM_ADD(17) RAM_ADD(18) /IDDTN STAT_OUT CTRL_IN
Ball
AG2 AB6 AE3 AC5 AH2 AD4 AD6 AG3 AE4 AD5 AE5 AF4 AJ1 AK2 AG5 AF6 AF7 AG6 AH4 AE7 AG7 AJ3 AF8 AH6 AE9 AJ4 AE10 AJ5 AF9 C2 J6 AH1 AF12 G5 K6 E2
Signal Name
SE_D_IN20(0) SE_D_IN20(1) SE_D_IN20(2) SE_D_IN20(3) SE_D_IN21(0) SE_D_IN21(1) SE_D_IN21(2) SE_D_IN21(3) SE_D_IN22(0) SE_D_IN22(1) SE_D_IN22(2) SE_D_IN22(3) SE_D_IN23(0) SE_D_IN23(1) SE_D_IN23(2) SE_D_IN23(3) SE_D_IN24(0) SE_D_IN24(1) SE_D_IN24(2) SE_D_IN24(3) SE_D_IN25(0) SE_D_IN25(1) SE_D_IN25(2) SE_D_IN25(3) SE_D_IN26(0) SE_D_IN26(1) SE_D_IN26(2) SE_D_IN26(3) SE_D_IN27(0) SE_D_IN27(1) SE_D_IN27(2) SE_D_IN27(3) SE_D_IN28(0) SE_D_IN28(1) SE_D_IN28(2) SE_D_IN28(3)
Ball
M3 J2 N4 G1 L2 N3 P6 N5 M2 L1 P5 N2 P4 R4 P3 P1 R2 T2 R1 U1 T4 W1 T5 V2 Y1 U4 T6 U5 V3 W2 AA1 V5 Y2 W3 AC1 AD1
Signal Name
SE_D_OUT25(1) SE_D_OUT25(2) SE_D_OUT25(3) SE_D_OUT26(0) SE_D_OUT26(1) SE_D_OUT26(2) SE_D_OUT26(3) SE_D_OUT27(0) SE_D_OUT27(1) SE_D_OUT27(2) SE_D_OUT27(3) SE_D_OUT28(0) SE_D_OUT28(1)) SE_D_OUT28(2) SE_D_OUT28(3) SE_D_OUT29(0) SE_D_OUT29(1) SE_D_OUT29(2) SE_D_OUT29(3) SE_D_OUT30(0) SE_D_OUT30(1) SE_D_OUT30(2) SE_D_OUT30(3) SE_D_OUT31(0) SE_D_OUT31(1) SE_D_OUT31(2) SE_D_OUT31(3) /OE RESET SE_SOC_IN(0) SE_SOC_IN(1) SE_SOC_IN(2) SE_SOC_IN(3) SE_SOC_IN(4) SE_SOC_IN(5) SE_SOC_IN(6)
Ball
AJ19 AE16 AF18 AG17 AF16 AJ18 AF17 AK19 AK17 AH17 AG16 AG15 AK15 AK14 AK16 AH14 AJ13 AF15 AK12 AF14 AE15 AG14 AK11 AK10 AJ12 AH13 AE14 D3 AF13 B22 C18 A20 D16 B15 A12 D14
Signal Name
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Ball
R28 N30 K29 M27 E30 G28 E28 B29 D27 F25 C26 A26 C24 B21 D19 A18 C16 C15 A13 B10 D12 A5 C7 C5 Y20 W19 U19 P19 M19 L20 W17 U17 P17 M17 W14 U14
61
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Table 14. Signal Locations (Signal Name to Ball) (Continued) Signal Name
/ACK ADD(0) ADD(1) ADD(2) ADD(3) ADD(4) ADD(5) ADD(6) ADD(7) /CS DATA(0) DATA(1) DATA(2) DATA(3) DATA(4) DATA(5) DATA(6) DATA(7) /INTR /RD /WR /PLL_BYPASS PLL_VDD PLL_VSS not used /SCAN_EN /SCAN_TRST SCAN_TCK SCAN_TDI SCAN_TDO SCAN_TMS SE_CLK_BYPASS SE_CLK SE_D_IN00(0) SE_D_IN00(1) SE_D_IN00(2)
Ball
AJ11 AK3 AG9 AH8 AK4 AF10 AG10 AH9 AJ7 AK7 AK6 AF11 AJ8 AE12 AE13 AG11 AH10 AJ9 AG13 AK8 AH12 P25 AJ30 AF27 H5 G6 E4 G4 B1 F5 F4 AF25 AJ16 E19 D20 A23
Signal Name
SE_D_IN29(0) SE_D_IN29(1) SE_D_IN29(2) SE_D_IN29(3) SE_D_IN30(0) SE_D_IN30(1) SE_D_IN30(2) SE_D_IN30(3) SE_D_IN31(0) SE_D_IN31(1) SE_D_IN31(2) SE_D_IN31(3) SE_D_OUT00(0) SE_D_OUT00(1) SE_D_OUT00(2) SE_D_OUT00(3) SE_D_OUT01(0) SE_D_OUT01(1) SE_D_OUT01(2) SE_D_OUT01(3) SE_D_OUT02(0) SE_D_OUT02(1) SE_D_OUT02(2) SE_D_OUT02(3) SE_D_OUT03(0) SE_D_OUT03(1) SE_D_OUT03(2) SE_D_OUT03(3) SE_D_OUT04(0) SE_D_OUT04(1) SE_D_OUT04(2) SE_D_OUT04(3) SE_D_OUT05(0) SE_D_OUT05(1) SE_D_OUT05(2) SE_D_OUT05(3)
Ball
AB2 AA3 Y4 V6 AC2 Y5 AE1 AD2 AA4 AA5 AG1 AC3 P26 L30 M29 R25 R27 P27 R26 N29 R29 M30 P30 P28 T30 U30 R30 T29 U28 V29 T26 W30 U26 T25 U27 Y30
Signal Name
SE_SOC_IN(7) SE_SOC_IN(8) SE_SOC_IN(9) SE_SOC_IN(10) SE_SOC_IN(11) SE_SOC_IN(12) SE_SOC_IN(13) SE_SOC_IN(14) SE_SOC_IN(15) SE_SOC_IN(16) SE_SOC_IN(17) SE_SOC_IN(18) SE_SOC_IN(19) SE_SOC_IN(20) SE_SOC_IN(21) SE_SOC_IN(22) SE_SOC_IN(23) SE_SOC_IN(24) SE_SOC_IN(25) SE_SOC_IN(26) SE_SOC_IN(27) SE_SOC_IN(28) SE_SOC_IN(29) SE_SOC_IN(30) SE_SOC_IN(31) SE_SOC_OUT0 SE_SOC_OUT1 SE_SOC_OUT2 SE_SOC_OUT3 SE_SOC_OUT4 SE_SOC_OUT5 SE_SOC_OUT6 SE_SOC_OUT7 RAM_ADD(0) RAM_ADD(1) RAM_ADD(2)
Ball
B12 C12 C10 E11 E10 E9 C6 C4 A2 J5 D1 F1 H1 K1 R6 R5 M1 T1 U3 U6 V4 W5 W6 AB3 AB4 N26 T27 AC30 AB27 AG25 AG21 AK24 AJ15 G26 G27 G25
Signal Name
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
Ball
P14 M14 Y11 W12 U12 P12 M12 L11 W21 AA12 M10 K19 P10 U10 W10 K12 K14 AA14 K17 AA17 AA19 M21 P21 U21 A1 C3 E5 F2 H4 J1 L3 P2 U2 AB1 Y3 AE2
62
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Table 14. Signal Locations (Signal Name to Ball) (Continued) Signal Name
SE_D_IN00(3) SE_D_IN01(0) SE_D_IN01(1) SE_D_IN01(2) SE_D_IN01(3) SE_D_IN02(0) SE_D_IN02(1) SE_D_IN02(2) SE_D_IN02(3) SE_D_IN03(0) SE_D_IN03(1) SE_D_IN03(2) SE_D_IN03(3) SE_D_IN04(0) SE_D_IN04(1) SE_D_IN04(2) SE_D_IN04(3) SE_D_IN05(0) SE_D_IN05(1) SE_D_IN05(2) SE_D_IN05(3) SE_D_IN06(0) SE_D_IN06(1) SE_D_IN06(2) SE_D_IN06(3) SE_D_IN07(0) SE_D_IN07(1) SE_D_IN07(2) SE_D_IN07(3) SE_D_IN08(0) SE_D_IN08(1) SE_D_IN08(2) SE_D_IN08(3) SE_D_IN09(0) SE_D_IN09(1) SE_D_IN09(2)
Ball
C19 D18 A24 A21 B20 F17 E18 F16 B19 E17 B18 E16 D17 C17 A17 A19 B16 A16 A14 A15 D15 E15 B13 C14 A11 F15 E14 F14 C13 A10 E13 D13 B11 A8 A7 E12
Signal Name
SE_D_OUT06(0) SE_D_OUT06(1) SE_D_OUT06(2) SE_D_OUT06(3) SE_D_OUT07(0) SE_D_OUT07(1) SE_D_OUT07(2) SE_D_OUT07(3) SE_D_OUT08(0) SE_D_OUT08(1) SE_D_OUT08(2) SE_D_OUT08(3) SE_D_OUT09(0) SE_D_OUT09(1) SE_D_OUT09(2) SE_D_OUT09(3) SE_D_OUT10(0) SE_D_OUT10(1) SE_D_OUT10(2) SE_D_OUT10(3) SE_D_OUT11(0) SE_D_OUT11(1) SE_D_OUT11(2) SE_D_OUT11(3) SE_D_OUT12(0) SE_D_OUT12(1) SE_D_OUT12(2) SE_D_OUT12(3) SE_D_OUT13(0) SE_D_OUT13(1) SE_D_OUT13(2) SE_D_OUT13(3) SE_D_OUT14(0) SE_D_OUT14(1) SE_D_OUT14(2) SE_D_OUT14(3)
Ball
AA30 W29 V28 U25 W28 Y29 V27 V26 AA28 AB29 W26 AD30 AC29 W25 V25 Y27 AB28 AD29 AE30 Y26 AC28 AG30 AA26 AA27 AA25 AF29 AB26 AH30 AC26 AE28 AB25 AG29 AG28 AD25 AD27 AH29
Signal Name
RAM_ADD(3) RAM_ADD(4) RAM_ADD(5) RAM_ADD(6) RAM_ADD(7) RAM_ADD(8) RAM_ADD(9) RAM_ADD(10) RAM_ADD(11) RAM_ADD(12) RAM_ADD(13) RAM_ADD(14) RAM_ADD(15) RAM_CLK RAM_DATA(0) RAM_DATA(1) RAM_DATA(2) RAM_DATA(3) RAM_DATA(4) RAM_DATA(5) RAM_DATA(6) RAM_DATA(7) RAM_DATA(8) RAM_DATA(9) RAM_DATA(10) RAM_DATA(11) RAM_DATA(12) RAM_DATA(13) RAM_DATA(14) RAM_DATA(15) /RAM_OE /RAM_WR /TEST_MODE GND GND GND
Ball
E27 F27 F26 B30 A29 E25 D25 D26 F24 D24 E24 E23 C27 B23 F22 B28 F21 B26 C25 A28 B27 C23 E22 E21 D21 D22 B24 A27 E20 C22 C21 A25 N28 B2 D4 F6
Signal Name
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
Ball
AC4 AK1 AH3 AF5 AJ6 AG8 AK9 AH11 AJ14 AJ17 AK22 AH20 AJ25 AG23 AK30 AH28 AF26 AE29 AC27 AB30 Y28 U29 P29 J30 L28 F29 H27 A30 C28 E26 B25 D23 A22 C20 B17 B14
63
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Table 14. Signal Locations (Signal Name to Ball) (Continued) Signal Name
SE_D_IN09(3) SE_D_IN10(0) SE_D_IN10(1) SE_D_IN10(2) SE_D_IN10(3) SE_D_IN11(0)
Ball
B9 D11 F13 F12 B8 A6
Signal Name
SE_D_OUT15(0) SE_D_OUT15(1) SE_D_OUT15(2) SE_D_OUT15(3) SE_D_OUT16(0) SE_D_OUT16(1)
Ball
AK29 AE26 AD26 AE27 AF24 AG24
Signal Name
GND GND GND GND GND GND
Ball
E3 E1 G3 K2 M4 N1
Signal Name
VDD VDD VDD VDD RAM_ADD(16) RAM_PARITY
Ball
A9 C11 B6 D8 F19 F18
64
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616 6.3 Signal Locations (Ball to Signal Name)
Issue 3
Table 15. Signal Locations (Ball to Signal Name) Ball
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 B1 B2 B3 B4 B5
Signal Name
VDD SE_SOC_IN15 SE_D_IN12(3) SE_D_IN12(0) GND SE_D_IN11(0) SE_D_IN09(1) SE_D_IN09(0) VDD SE_D_IN08(0) SE_D_IN06(3) SE_SOC_IN05 GND SE_D_IN05(1) SE_D_IN05(2) SE_D_IN05(0) SE_D_IN04(1) GND SE_D_IN04(2) SE_SOC_IN02 SE_D_IN01(2) VDD SE_D_IN00(2) SE_D_IN01(1) /RAM_WR GND RAM_DATA(13) RAM_DATA(5) RAM_ADD(7) VDD SCAN_TDI GND SE_D_IN14(1) SE_D_IN13(2) SE_D_IN13(0)
Ball
F1 F2 F3 F4 F5 F6 F7 F9 F10 F12 F13 F14 F15 F16 F17 F18 F19 F21 F22 F24 F25 F26 F27 F28 F29 F30 G1 G2 G3 G4 G5 G6 G25 G26 G27
Signal Name
SE_SOC_IN18 VDD SE_D_IN16(0) SCAN_TMS SCAN_TDO GND SE_D_IN14(3) SE_D_IN13(3) SE_D_IN13(1) SE_D_IN10(2) SE_D_IN10(1) SE_D_IN07(2) SE_D_IN07(0) SE_D_IN02(2) SE_D_IN02(0) RAM_PARITY RAM_ADD(16) RAM_DATA(2) RAM_DATA(0) RAM_ADD(11) GND RAM_ADD(5) RAM_ADD(4) BP_ACK_IN(25) VDD BP_ACK_IN(11) SE_D_IN20(3) SE_D_IN17(3) GND SCAN_TCK /IDDTN /SCAN_EN RAM_ADD(2) RAM_ADD(0) RAM_ADD(1)
Ball
T3 T4 T5 T6 T25 T26 T27 T28 T29 T30 U1 U2 U3 U4 U5 U6 U10 U12 U14 U17 U19 U21 U25 U26 U27 U28 U29 U30 V1 V2 V3 V4 V5 V6 V25
Signal Name)
GND SE_D_IN25(0) SE_D_IN25(2) SE_D_IN26(2) SE_D_OUT05(1) SE_D_OUT04(2) SE_SOC_OUT1 GND SE_D_OUT03(3) SE_D_OUT03(0) SE_D_IN24(3) VDD SE_SOC_IN25 SE_D_IN26(1) SE_D_IN26(3) SE_SOC_IN26 GND GND GND GND GND GND SE_D_OUT06(3) SE_D_OUT05(0) SE_D_OUT05(2) SE_D_OUT04(0) VDD SE_D_OUT03(1) GND SE_D_IN25(3) SE_D_IN27(0) SE_SOC_IN27 SE_D_IN27(3) SE_D_IN29(3) SE_D_OUT09(2)
all
AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9
Signal Name
VDD BP_ACK_OUT(18) BP_ACK_OUT(19) BP_ACK_OUT(25) BP_ACK_OUT(31) ADD(4) DATA(1) RAM_ADD(18) RESET SE_D_OUT30(0) SE_D_OUT29(2) SE_D_OUT26(1) SE_D_OUT26(3) SE_D_OUT25(3) SE_D_OUT22(1) SE_D_OUT20(0) SE_D_OUT19(0) SE_D_OUT19(1) SE_D_OUT17(3) SE_D_OUT16(0) SE_CLK_BYPASS VDD PLL_VSS GND SE_D_OUT12(1) GND SE_D_IN31(2) BP_ACK_OUT(3) BP_ACK_OUT(10) GND BP_ACK_OUT(17) BP_ACK_OUT(20) BP_ACK_OUT(23) VDD ADD(1)
65
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Table 15. Signal Locations (Ball to Signal Name) (Continued) Ball
B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11
Signal Name
VDD SE_D_IN11(1) SE_D_IN10(3) SE_D_IN09(3) GND SE_D_IN08(3) SE_SOC_IN07 SE_D_IN06(1) VDD SE_SOC_IN04 SE_D_IN04(3) VDD SE_D_IN03(1) SE_D_IN02(3) SE_D_IN01(3) GND SE_SOC_IN00 RAM_CLK RAM_DATA(12) VDD RAM_DATA(3) RAM_DATA(6) RAM_DATA(1) GND RAM_ADD(6) SE_D_IN16(1) CELL_24_START VDD SE_SOC_IN14 GND SE_SOC_IN13 GND SE_D_IN12(1) SE_D_IN11(2) SE_SOC_IN09 VDD
Ball
G28 G29 G30 H1 H2 H3 H4 H5 H26 H27 H28 H29 H30 J1 J2 J3 J4 J5 J6 J25 J26 J27 J28 J29 J30 K1 K2 K3 K4 K5 K6 K12 K14 K17 K19 K25
Signal Name
GND BP_ACK_IN(17) BP_ACK_IN(2) SE_SOC_IN19 SE_D_IN19(1) SE_D_IN16(3) VDD not used BP_ACK_IN(31) VDD BP_ACK_IN(22) BP_ACK_IN(9) BP_ACK_IN(6) VDD SE_D_IN20(1) SE_D_IN18(1) SE_D_IN17(2) SE_SOC_IN16 CELL_START BP_ACK_IN(29) BP_ACK_IN(21) BP_ACK_IN(18) BP_ACK_IN(14) BP_ACK_IN(4) VDD SE_SOC_IN20 GND SE_D_IN19(0) SE_D_IN17(1) SE_D_IN17(0) STAT_OUT GND GND GND GND BP_ACK_IN(27)
Ball
V26 V27 V28 V29 V30 W1 W2 W3 W4 W5 W6 W10 W12 W14 W17 W19 W21 W25 W26 W27 W28 W29 W30 Y1 Y2 Y3 Y4 Y5 Y11 Y20 Y26 Y27 Y28 Y29 Y30 AA1
Signal Name)
SE_D_OUT07(3) SE_D_OUT07(2) SE_D_OUT06(2) SE_D_OUT04(1) GND SE_D_IN25(1) SE_D_IN27(1) SE_D_IN28(1) GND SE_SOC_IN28 SE_SOC_IN29 GND GND GND GND GND GND SE_D_OUT09(1) SE_D_OUT08(2) GND SE_D_OUT07(0) SE_D_OUT06(1) SE_D_OUT04(3) SE_D_IN26(0) SE_D_IN28(0) VDD SE_D_IN29(2) SE_D_IN30(1) GND GND SE_D_OUT10(3) SE_D_OUT09(3) VDD SE_D_OUT07(1) SE_D_OUT05(3) SE_D_IN27(2)
all
AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15
Signal Name
ADD(5) DATA(5) GND /INTR SE_D_OUT30(2) SE_D_OUT28(0) SE_D_OUT27(3) SE_D_OUT26(0) SE_D_OUT23(0) GND SE_D_OUT22(0) SE_SOC_OUT5 SE_D_OUT20(3) VDD SE_D_OUT16(1) SE_SOC_OUT4 SE_D_OUT16(3) GND SE_D_OUT14(0) SE_D_OUT13(3) SE_D_OUT11(1) RAM_ADD(17) BP_ACK_OUT(7) VDD BP_ACK_OUT(21) GND BP_ACK_OUT(26) GND ADD(2) ADD(6) DATA(6) VDD /WR SE_D_OUT31(2) SE_D_OUT29(0) GND
66
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Table 15. Signal Locations (Ball to Signal Name) (Continued) Ball
C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
Signal Name
SE_SOC_IN08 SE_D_IN07(3) SE_D_IN06(2) GND GND SE_D_IN04(0) SE_SOC_IN01 SE_D_IN00(3) VDD /RAM_OE RAM_DATA(15) RAM_DATA(7) GND RAM_DATA(4) GND RAM_ADD(15) VDD BP_ACK_IN(28) BP_ACK_IN(24) SE_SOC_IN17 SE_D_IN16(2) /OE GND SE_D_IN15(3) SE_D_IN15(0) SE_D_IN14(2) VDD SE_D_IN12(2) SE_D_IN11(3) SE_D_IN10(0) GND SE_D_IN08(2) SE_SOC_IN06 SE_D_IN05(3) SE_SOC_IN03 SE_D_IN03(3)
Ball
K26 K27 K28 K29 K30 L1 L2 L3 L4 L5 L11 L20 L26 L27 L28 L29 L30 M1 M2 M3 M4 M5 M6 M10 M12 M14 M17 M19 M21 M25 M26 M27 M28 M29 M30 N1
Signal Name
BP_ACK_IN(20) BP_ACK_IN(19) BP_ACK_IN(10) GND BP_ACK_IN(1) SE_D_IN22(1) SE_D_IN21(0) VDD SE_D_IN19(3) SE_D_IN18(0) GND GND BP_ACK_IN(15) BP_ACK_IN(7) VDD BP_ACK_IN(0) SE_D_OUT00(1) SE_SOC_IN23 SE_D_IN22(0) SE_D_IN20(0) GND SE_D_IN19(2) SE_D_IN18(2) GND GND GND GND GND GND BP_ACK_IN(13) BP_ACK_IN(8) GND BP_ACK_IN(5) SE_D_OUT00(2) SE_D_OUT02(1) GND
Ball
AA2 AA3 AA4 AA5 AA6 AA12 AA14 AA17 AA19 AA25 AA26 AA27 AA28 AA29 AA30 AB1 AB2 AB3 AB4 AB5 AB6 AB25 AB26 AB27 AB28 AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC26 AC27 AC28 AC29
Signal Name)
GND SE_D_IN29(1) SE_D_IN31(0) SE_D_IN31(1) BP_ACK_OUT(2) GND GND GND GND SE_D_OUT12(0) SE_D_OUT11(2) SE_D_OUT11(3) SE_D_OUT08(0) GND SE_D_OUT06(0) VDD SE_D_IN29(0) SE_SOC_IN30 SE_SOC_IN31 BP_ACK_OUT(0) BP_ACK_OUT(4) SE_D_OUT13(2) SE_D_OUT12(2) SE_SOC_OUT3 SE_D_OUT10(0) SE_D_OUT08(1) VDD SE_D_IN28(2) SE_D_IN30(0) SE_D_IN31(3) VDD BP_ACK_OUT(6) SE_D_OUT13(0) VDD SE_D_OUT11(0) SE_D_OUT09(0)
all
AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21
Signal Name
GND SE_D_OUT27(2) SE_D_OUT24(1) SE_D_OUT23(2) VDD SE_D_OUT22(3) SE_D_OUT21(3) SE_D_OUT19(2) GND SE_D_OUT18(1) GND SE_D_OUT17(2) VDD SE_D_OUT14(3) SE_D_OUT12(3) BP_ACK_OUT(15) GND BP_ACK_OUT(24) BP_ACK_OUT(28) BP_ACK_OUT(30) VDD ADD(7) DATA(2) DATA(7) GND /ACK SE_D_OUT31(1) SE_D_OUT29(1) VDD SE_SOC_OUT7 SE_CLK VDD SE_D_OUT26(2) SE_D_OUT25(1) SE_D_OUT24(2) GND
67
Released Datasheet
PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Table 15. Signal Locations (Ball to Signal Name) (Continued) Ball
D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23
Signal Name
SE_D_IN01(0) GND SE_D_IN00(1) RAM_DATA(10) RAM_DATA(11) VDD RAM_ADD(12) RAM_ADD(9) RAM_ADD(10) GND BP_ACK_IN(30) BP_ACK_IN(23) BP_ACK_IN(16) GND CTRL_IN GND /SCAN_TRST VDD SE_D_IN15(2) SE_D_IN15(1) SE_D_IN14(0) SE_SOC_IN12 SE_SOC_IN11 SE_SOC_IN10 SE_D_IN09(2) SE_D_IN08(1) SE_D_IN07(1) SE_D_IN06(0) SE_D_IN03(2) SE_D_IN03(0) SE_D_IN02(1) SE_D_IN00(0) RAM_DATA(14) RAM_DATA(9) RAM_DATA(8) RAM_ADD(14)
Ball
N2 N3 N4 N5 N6 N25 N26 N27 N28 N29 N30 P1 P2 P3 P4 P5 P6 P10 P12 P14 P17 P19 P21 P25 P26 P27 P28 P29 P30 R1 R2 R3 R4 R5 R6 R25
Signal Name
SE_D_IN22(3) SE_D_IN21(1) SE_D_IN20(2) SE_D_IN21(3) SE_D_IN18(3) BP_ACK_IN(12) SE_SOC_OUT0 BP_ACK_IN(3) /TEST_MODE SE_D_OUT01(3) GND SE_D_IN23(3) VDD SE_D_IN23(2) SE_D_IN23(0) SE_D_IN22(2) SE_D_IN21(2) GND GND GND GND GND GND /PLL_BYPASS SE_D_OUT00(0) SE_D_OUT01(1) SE_D_OUT02(3) VDD SE_D_OUT02(2) SE_D_IN24(2) SE_D_IN24(0) GND SE_D_IN23(1) SE_SOC_IN22 SE_SOC_IN21 SE_D_OUT00(3)
Ball
AC30 AD1 AD2 AD3 AD4 AD5 AD6 AD25 AD26 AD27 AD28 AD29 AD30 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE9 AE10 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE21 AE22 AE24 AE25 AE26 AE27
Signal Name)
SE_SOC_OUT2 SE_D_IN28(3) SE_D_IN30(3) GND BP_ACK_OUT(8) BP_ACK_OUT(12) BP_ACK_OUT(9) SE_D_OUT14(1) SE_D_OUT15(2) SE_D_OUT14(2) GND SE_D_OUT10(1) SE_D_OUT08(3) SE_D_IN30(2) VDD BP_ACK_OUT(5) BP_ACK_OUT(11) BP_ACK_OUT(13) GND BP_ACK_OUT(22) BP_ACK_OUT(27) BP_ACK_OUT(29) DATA(3) DATA(4) SE_D_OUT31(3) SE_D_OUT30(1) SE_D_OUT25(2) SE_D_OUT24(0) SE_D_OUT21(1) SE_D_OUT21(2) SE_D_OUT18(3) SE_D_OUT17(1) SE_D_OUT16(2) GND SE_D_OUT15(1) SE_D_OUT15(3)
all
AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27
Signal Name
SE_D_OUT23(1) SE_D_OUT22(2) SE_D_OUT20(2) VDD SE_D_OUT18(2) SE_D_OUT19(3) SE_D_OUT17(0) GND PLL_VDD VDD BP_ACK_OUT(16) ADD(0) ADD(3) GND DATA(0) /CS /RD VDD SE_D_OUT31(0) SE_D_OUT30(3) SE_D_OUT29(3) GND SE_D_OUT28(2) SE_D_OUT28(1) SE_D_OUT28(3) SE_D_OUT27(1) GND SE_D_OUT27(0) SE_D_OUT25(0) SE_D_OUT24(3) VDD SE_D_OUT23(3) SE_SOC_OUT6 SE_D_OUT21(0) GND SE_D_OUT20(1)
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
Table 15. Signal Locations (Ball to Signal Name) (Continued) Ball
E24 E25 E26 E27 E28 E29 E30
Signal Name
RAM_ADD(13) RAM_ADD(8) VDD RAM_ADD(3) GND BP_ACK_IN(26) GND
Ball
R26 R27 R28 R29 R30 T1 T2
Signal Name
SE_D_OUT01(2) SE_D_OUT01(0) GND SE_D_OUT02(0) SE_D_OUT03(2) SE_SOC_IN24 SE_D_IN24(1)
Ball
AE28 AE29 AE30 AF1 AF2 AF3 AF4
Signal Name)
SE_D_OUT13(1) VDD SE_D_OUT10(2) GND BP_ACK_OUT(1) GND BP_ACK_OUT(14)
all
AK28 AK29 AK30
Signal Name
SE_D_OUT18(0) SE_D_OUT15(0) VDD
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Long Form Data Sheet
PMC-980616
Issue 3
6.4 Pin Descriptions All inputs except SE_CLK are 5V tolerant. All bidirectional signals are 5 V tolerant. Other outputs are not 5 V tolerant. All pins have pull-ups except /IDDTN. All inputs have Schmitt triggers, except the SCAN_TDI, SCAN_TMS, /SCAN_TRST, /SCAN_EN, /TEST_MODE, /PLL_BYPASS, DATA[7:0] (which is a bi-di) and RAM_DATA[15:0] (which is also a bi-di).
For outputs, the drive strength listed in the "Type" column (in Table 16 on page 72 through Table 20 on page 81) is in milliamperes. (For example, Out 5 is and output with a drive strength of 5mA.) All switch fabric interface outputs, namely SE_SOC_OUT, SE_D_OUT and BP_ACK_OUT, should be series terminated if the trace is more than four inches long. (Use the series termination resistor as close as possible to the QSE. If the characteristic impedance of the board trace is R ohms, then use a series termination of (R-11) ohms for SE_SOC_OUT, and (R-17) ohms for SE_D_OUT and BP_ACK_OUT .)
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PMC-980616 Figure 36 shows the signal groupings for the QSE.
Issue 3
SE_CLK SE_CLK_BYPASS /PLL_BYPASS
RESET /OE ADD(7:0) DATA(7:0)
CELL_START CELL_24_START CTRL_IN STAT_OUT
/CS /RD /WR /ACK /INTR
Processor Interface
SE_SOC_IN(0) SE_D_IN(0,3:0) BP_ACK_OUT(0)
SE_SOC_OUT(0) (Shared between ports 0-3) SE_D_OUT(0,3:0) QSE PM73488 BP_ACK_IN(0) Output Ports
Input Ports SE_SOC_IN(31) SE_D_IN(31,3:0) BP_ACK_OUT(31)
SE_SOC_OUT(7) (Shared between ports 28-31) SE_D_OUT(31,3:0) BP_ACK_IN(31) RAM_ADDR(18:0) RAM_DATA(15:0) RAM_PARITY RAM_CLK /RAM_OE /RAM_WR
Boundary Scan Interface
SCAN_TCK SCAN_TDI SCAN_TDO SCAN_TMS /SCAN_TRST /SCAN_EN
SRAM Interface
/TEST_MODE /IDDTN
Figure 36. QSE Pinout Block Diagram
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PMC-980616 6.4.1 Processor Interface Signals
Issue 3
Table 16. Processor Interface Signals (21 Signal Pins) Signal Name Ball # AJ7, AH9, AG10, AF10, AK4, AH8, AG9, AK3 AJ9, AH10, AG11, AE13, AE12, AJ8, AF11, AK6 AK7 AK8 AH12 AJ11 AG13 # of Pins 8 Type In Description Address Bits 7to 0 are part of the 8-bit processor address bus. Data Bits 7 to 0 are part of the 8-bit processor data bus.
ADD(7:0)
DATA(7:0)
8
Bi 3
/CS
1 1 1 1 1
In In In Out 5 Out 5
Chip Select is an active low signal that selects the device for processor access. Read is an active low signal that selects a read cycle. Write is an active low signal that selects a write cycle. Acknowledge is an active low signal that indicates the processor cycle is finished. Interrupt indicates an interrupt is present.
/RD
/WR
/ACK /INTR
6.4.2
Multicast RAM Interface Signals
Table 17. Multicast RAM Interface Signals (39 Signal Pins)
Signal Name
Ball # AF12, AH1, F18, C27, E23, E24, D24, F24, D26, D25, E25, A29, B30, F26, F27, E27, G25, G27, G26 C22, E20, A27, B24, D22, D21, E21, E22, C23, B27, A28, C25, B26, F21, B28, F22 F19 B23
# of Pins 19
Type Out 5
Description RAM Address Bits 18 to 0 are part of the 19-bit SRAM address bus.
RAM_ADD(18:0)
RAM_DATA(15:0)
16
Bi 3
RAM Data Bits 15 to 0 are part of the 16-bit SRAM data bus.
RAM_PARITY RAM_CLK
1 1
Bi 3 Out 8
Parity for the RAM Data bits. Generated and checked by the QSE. RAM Clock.
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PMC-980616 6.4.2 Multicast RAM Interface Signals
Issue 3
Table 17. Multicast RAM Interface Signals (39 Signal Pins) Signal Name Ball # C21 A25 # of Pins 1 1 Type Out 5 Out 5 Description RAM Output Enable enables all SRAM output signals. RAM Write Enable strobes data into external SRAM.
/RAM_OE
/RAM_WR
NOTE: The external RAM /CE and /ADSC signals are expected to be tied low and the external RAM /ADSP and /ADV signals are expected to be tied high.
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PMC-980616 6.4.3 QSE Interface Signals
Issue 3
Table 18. QSE Interface Signals (364 Signal Pins) Ball # J6 # of Pins 1 Type In Description The rising edge of Cell Start indicates to the QSE it should stop looking for the SE_SOC_IN(31:0) on the input ports. The signal must have the following characteristics: The rising edge should come every 118 clocks exactly. Also, it must be high for at least one clock and low for at least eight clocks during each 118-cycle period. Thus, Cell Start must be high for x clocks and low for (118-x) clocks, where 1x110. Cell 24 Start indicates the start of the 4Nth cell time. It should be driven high every 4N th CELL_START assertions, and should match CELL_START when driven high. Here, N can be any integer 1, as long as it is the same for all the QSE and QRT devices in the fabric. It is called CELL_24_START because N used to be 6 (so 4N used to be 24) in some legacy systems, but that is no longer relevant. Control In is used to feed in an information packet to the QSE. This information packet can be used to tell the QSE not to accept any incoming cells (which is called a "/No Data In" command) and/or tell it not to send any cells to the next stage (which is called a "/No Data Out" command). There is a software configurable mode which splits the "/No Data In" and "/No Data Out" functionality and assigns them to separate pins. If this mode is turned on, then the CTRL_IN pin performs the "/No Data Out" functionality. (The complementary function of "/No Data In" is performed by the STAT_OUT pin; see below.) That is, whenever CTRL_IN is pulled low, the QSE will not send any cells to the next stage. After Reset, the above mode is on by default; that is, the CTRL_IN pin is configured as "/No Data Out".
Signal Name
CELL_START
CELL_24_START
C2
1
In
CTRL_IN (or /No_Data_Out)
E2
1
In
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Table 18. QSE Interface Signals (364 Signal Pins) (Continued) Ball # K6 # of Pins 1 Type Bi 3 Description On this pin, the QSE periodically puts out an information packet which indicates if all multicast buffers are empty or not. There is a software configurable mode in which the STAT_OUT pin ceases to be an output pin, and instead turns into an input pin that performs "/No Data In" functionality. (The complementary funcion of "/No Data Out" is performed by the CTRL_IN pin; see above). That is, whenever STAT_OUT is pulled low, the QSE will not accept any incoming cell. After Reset, the above mode is on by default; that is, the STAT_OUT pin is configured as "/No Data In". AB4, AB3, W6, W5, V4, U6, U3, T1, M1, R5, R6, K1, H1, F1, D1, J5, A2, C4, C6, E9, E10, E11, C10, C12, B12, D14, A12, B15, D16, A20, C18, B22 32 In Receive Cell Start indicates the start of a cell time. This signal precedes the first nibble of a cell by one clock.
Signal Name
STAT_OUT (or /No_Data_In)
SE_SOC_IN(31:0)
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Table 18. QSE Interface Signals (364 Signal Pins) (Continued) Ball # (As follows) AC3, AG1, AA5, AA4 AD2, AE1, Y5, AC2 V6, Y4, AA3, AB2 AD1, AC1, W3, Y2 V5, AA1, W2, V3 U5, T6, U4, Y1 V2, T5, W1, T4 U1, R1, T2, R2 P1, P3, R4, P4 N2, P5, L1, M2 N5, P6, N3, L2 G1, N4, J2, M3 L4, M5, H2, K3 N6, M6, J3, L5 G2, J4, K4, K5 H3, D2, C1, F3 D5, E6, E7, D6 F7, D7, B3, E8 F9, B4, F10, B5 A3, D9, C8, A4 D10, C9, B7, A6 B8, F12, F13, D11 B9, E12, A7, A8 B11, D13, E13, A10 C13, F14, E14, F15 A11, C14, B13, E15 D15, A15, A14, A16 B16, A19, A17, C17 D17, E16, B18, E17 B19, F16, E18, F17 B20, A21, A24, D18 C19, A23, D20, E19 # of Pins 128 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Type In In In In In In In In In In In In In In In In In In In In In In In In In In In In In In In In In Description SE_D_In Ports 31-0, Bits 3 to 0 are the nibble-wide data path.
Signal Name
SE_D_IN(31:0, 3:0) SE_D_IN31(3:0) SE_D_IN30(3:0) SE_D_IN29(3:0) SE_D_IN28(3:0) SE_D_IN27(3:0) SE_D_IN26(3:0) SE_D_IN25(3:0) SE_D_IN24(3:0) SE_D_IN23(3:0) SE_D_IN22(3:0) SE_D_IN21(3:0) SE_D_IN20(3:0) SE_D_IN19(3:0) SE_D_IN18(3:0) SE_D_IN17(3:0) SE_D_IN16(3:0) SE_D_IN15(3:0) SE_D_IN14(3:0) SE_D_IN13(3:0) SE_D_IN12(3:0) SE_D_IN11(3:0) SE_D_IN10(3:0) SE_D_IN09(3:0) SE_D_IN08(3:0) SE_D_IN07(3:0) SE_D_IN06(3:0) SE_D_IN05(3:0) SE_D_IN04(3:0) SE_D_IN03(3:0) SE_D_IN02(3:0) SE_D_IN01(3:0) SE_D_IN00(3:0)
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Issue 3
Table 18. QSE Interface Signals (364 Signal Pins) (Continued) Ball # AF9, AJ5, AE10, AJ4, AE9, AH6, AF8, AJ3, AG7, AE7, AH4, AG6, AF7, AF6, AG5, AK2, AJ1, AF4, AE5, AD5, AE4, AG3, AD6, AD4, AH2, AC5, AE3, AB6, AG2, AA6, AF2, AB5 AJ15, AK24, AG21, AG25, AB27, AC30, T27, N26 # of Pins 32 Type Out 5 Description Acknowledge Outputs 31 to 0 assert an acknowledge toward the previous QSE or QRT for unicast cells. It also carries backpressure information for multicast cells.
Signal Name
BP_ACK_OUT(31:0)
SE_SOC_OUT(7:0)
8
Out 8
Transmit Cell Start indicates the start of a cell time. This signal precedes the first nibble of a cell by one clock.
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Issue 3
Table 18. QSE Interface Signals (364 Signal Pins) (Continued) Ball # (As follows) AE14, AH13, AJ12, AK10 AK11, AG14, AE15, AF14 AK12, AF15, AJ13, AH14 AK16, AK14, AK15, AG15 AG16, AH17, AK17, AK19 AF17, AJ18, AF16, AG17 AF18, AE16, AJ19, AK20 AK21, AJ20, AH18, AE17 AK23, AH19, AJ22, AG18 AH21, AJ23, AF19, AG20 AH22, AE19, AE18, AK25 AG22, AJ24, AK27, AF20 AJ27, AH23, AF22, AF21 AE21, AJ26, AH25, AK28 AF23, AH27, AE22, AJ28 AG26, AE24, AG24, AF24 # of Pins 128 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Type Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Description SE_D_Out Ports 31-0, Bits 3 to 0 are 32 nibble-wide output ports.
Signal Name
SE_D_OUT(31:0, 3:0) SE_D_OUT31(3:0) SE_D_OUT30(3:0)
SE_D_OUT29(3:0) SE_D_OUT28(3:0) SE_D_OUT27(3:0) SE_D_OUT26(3:0) SE_D_OUT25(3:0) SE_D_OUT24(3:0)
SE_D_OUT23(3:0) SE_D_OUT22(3:0) SE_D_OUT21(3:0) SE_D_OUT20(3:0)
SE_D_OUT19(3:0)
SE_D_OUT18(3:0) SE_D_OUT17(3:0)
SE_D_OUT16(3:0)
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Issue 3
Table 18. QSE Interface Signals (364 Signal Pins) (Continued) Ball # AE27, AD26, AE26, AK29 AH29, AD27, AD25, AG28 AG29, AB25, AE28, AC26 AH30, AB26, AF29, AA25 AA27, AA26, AG30, AC28 Y26, AE30, AD29, AB28 Y27, V25, W25, AC29 AD30, W26, AB29, AA28 V26, V27, Y29, W28 U25, V28, W29, AA30 Y30, U27, T25, U26 W30, T26, V29, U28 T29, R30, U30, T30 P28, P30, M30, R29 N29, R26, P27, R27 R25, M29, L30, P26 H26, D28, J25, C29, K25, E29, F28, C30, D29, H28, J26, K26, K27, J27, G29, D30, L26, J28, M25, N25, F30, K28, H29, M26, L27, H30, M28, J29, N27, G30, K30, L29 # of Pins 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 32 Type Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 Out 5 In Acknowledge Inputs 31 to 0 receive an acknowledge from the previous QSE or QRT for unicast cells. It also carries backpressure information for multicast cells. Description
Signal Name
SE_D_OUT15(3:0) SE_D_OUT14(3:0) SE_D_OUT13(3:0) SE_D_OUT12(3:0) SE_D_OUT11(3:0) SE_D_OUT10(3:0) SE_D_OUT09(3:0) SE_D_OUT08(3:0) SE_D_OUT07(3:0) SE_D_OUT06(3:0) SE_D_OUT05(3:0) SE_D_OUT04(3:0) SE_D_OUT03(3:0) SE_D_OUT02(3:0) SE_D_OUT01(3:0) SE_D_OUT00(3:0) BP_ACK_IN(31:0)
6.4.4
Boundary Scan Signals Table 19. Boundary Scan Signals (8 Signal Pins)
Signal Name
Ball # G4
Pin # 1
Type In
Description Scan Test Clock is an independent clock used to drive the internal boundary scan test logic. (Normal operation = VDD through a pull-up resistor.)
SCAN_TCK
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Table 19. Boundary Scan Signals (8 Signal Pins) (Continued)
Signal Name Ball # B1 Pin # 1 Type In Description Scan Test Data Input is the serial input for boundary scan test data and instruction bits. (Normal operation = VDD through a pull-up resistor.) Scan Test Data Output is the serial output for boundary scan test data. Scan Test Mode Select controls the operation of the internal boundary scan test logic. (Normal operation = VDD through a pull-up resistor.) Scan Test Reset is used to reset the internal boundary scan test logic. (Normal operation = VDD through a pull-up resistor.) Scan Test Enable is used to enable the internal scan test logic. (Normal operation = VDD through a pull-up resistor.) Test mode. (Normal operation = VDD through a pull-up resistor.)
SCAN_TDI
SCAN_TDO SCAN_TMS
F5 F4
1 1
Out 6 In
/SCAN_TRST
E4
1
In
/SCAN_EN
G6
1
In
/TEST_MODE
N28
1
In
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Issue 3
Table 20. Miscellaneous Signals (8 Signal Pins)
Signal Name Ball # AJ16 AF25 D3 AF13 Pin # 1 1 1 1 Type In In In In Description QSE Clock is the main QSE clock. QSE Bypass Clock is the clock used when the Phase Locked Loop (PLL) is bypassed. Output Enable is an active low signal that enables the drivers on device outputs. Reset is an active high signal used to initialize or reinitialize the device. SE_CLK must be present for the reset to take effect. Bypass PLL, and use clock from SE_CLK_BYPASS for the QSE instead of SE_CLK. (Normal operation = VDD through a pull-up resistor.) PLL power. Connect to VDD. PLL ground. Connect to GND. Global output disable. (Normal operation = GND.) Supply voltage 3.3 V 10%.
SE_CLK SE_CLK_BYPASS /OE
RESET
/PLL_BYPASS
P25
1
In
PLL_VDD PLL_VSS /IDDTN VDD
AJ30 AF27 G5 D8, B6, C11, A9, B14, B17, C20, A22, D23, B25, E26, C28, A30, H27, F29, L28, J30, P29, U29, Y28, AB30, AC27, AE29, AF26, AH28, AK30, AG23, AJ25, AH20, AK22, AJ17, AJ14, AH11, AK9, AG8, AJ6, AF5, AH3, AK1, AC4, AE2, Y3, AB1, U2, P2, L3, J1, H4, F2, E5, C3, A1,
1 1 1 52
In In In In
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Table 20. Miscellaneous Signals (8 Signal Pins)
Signal Name Ball # N1, M4, K2, G3, E1, E3, F6, D4, B2, U21, P21, M21, AA19, AA17, K17, AA14, K14, K12, W10, U10, P10, K19, M10, AA12, W21, L11, M12, P12, U12, W12, Y11, M14, P14, U14, W14, M17, P17, U17, W17, L20, M19, P19, U19, W19, Y20, C5, C7, A5, D12, B10, A13, C15, C16, A18, D19, B21, C24, A26, C26, F25, D27, B29, E28, G28, E30, M27, K29, N30, R28, T28, V30, W27, AA29, AD28, AF30, AF28, AE25, AG27, AJ29, AH26, AH24, AK26, AG19, AJ21, AK18, AH16, AH15, AK13, AG12, AJ10, AH7, AK5, AH5, AF3, AE6, AG4, AJ2, AD3, AF1, W4, AA2, V1, T3, R3 Pin # 104 Type In Ground. Description
VSS
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PMC-980616 6.4.6 Total Pin Count
Issue 3
Table 21. Pin Allocations Signal Name Pin # 21 39 364 8 8 440 52 104 596 In In Supply voltage 3.3 V 10%. Ground. Type Description
Total processor interface signals Total multicast RAM signals Total QSE interface signals Total boundary scan signals Total miscellaneous signals Total signal pins VDD
GND
Total pins
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7
PHYSICAL CHARACTERISTICS
Table 22. Absolute Maximum Ratings Parameter Supply voltage DC output current, per pin Storage temperature Junction operating temperature Input rise time Input fall time ESD tolerance Latch-up current Conditions With respect to GND All outputs Min -0.3 -12 -65 -40 Max 3.9 12 125 125 10 10 1 80 Unit V mA C C ns ns kV mA
Symbol V DD IOUT TSTG TJ tR tF
Table 23. Recommended Operating Conditions Parameter Supply voltage Input voltage Ambient operating temperature See note about junction operating temperature after Table 26 on page 85. Conditions Min 3.0 V SS - 0.5 -40 Typ 3.3 VDD 25 Max 3.6 V DD + 0.3 85 Unit V V C
Symbol VDD VI TA
tR tF
Input rise time Input fall time
1.5 1.5
2 2
ns ns
.
Table 24. DC Operating Conditions Parameter High-level TTL input voltage Low-level TTL input voltage High-level TTL output voltage |IOH| Specified DC drive current (in Signal Descriptions section) |IOL| Specified DC drive current (in Signal Descriptions section) 66 MHz clock rate 900 Conditions 5 V tolerant inputs Min 2.2 GND-0.3 2.4 Typ VDD 0.0 Max 5.5 0.8 Unit V V V
Symbol VIH VIL
VOH
VOL
Low-level TTL output voltage
0.4
V
ITYP
Typical operating current
mA
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Table 25. Capacitance Parameter Input capacitance Output capacitance Load capacitance
* *
Symbol CIN
Conditions
Min 1.5 1.5
Max 6 6 30
Unit pF pF pF
COUT
CLOAD
To meet timing on any output signal at 25oC.
NOTES:
Capacitance measured Sample tested only.
Table 26. Estimated Package Thermal Characteristics Parameter Junction-to-Case thermal resistance Junction-to-Ambient thermal resistance Junction-to-Ambient thermal resistance Junction-to-Ambient thermal resistance Junction-to-Ambient thermal resistance Still air 200 lfpm 400 lfpm 600 lfpm Condition Typ 2.5 12.0 10.2 9.4 8.9 Unit C/Watt C/Watt C/Watt C/Watt C/Watt
Symbol JC JA JA JA JA
NOTE: The junction temperature must be kept below 125C while the device is operating.
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8
TIMING DIAGRAMS
All signal names are described in section 6.4 "Pin Descriptions" starting on page 70. Unless otherwise indicated, all output timing delays assume a capacitive loading of 30 pF and that the internal PLL is enabled. The use of the internal PLL is controlled through the /PLL_BYPASS signal. It is recommended that the internal PLL remains enabled 8.1 Microprocessor Timing
A microprocessor cycle starts when the chip select (/CS) and either read (/RD) or write (/WR) are asserted. During read cycles, the QSE asserts /ACK to indicate data on the data bus is valid, and during write cycles the QSE asserts / ACK to indicate the write has finished and data can be removed from the bus. The microprocessor can terminate the current cycle at anytime. As shown in Figure 37, the QSE stops driving the data bus and deasserts the /ACK control line when the cycle terminates. The current cycle terminates when the chip select is deasserted, or when both read and write are deasserted. A new cycle can start once the /ACK has been deasserted. If the cycle was terminated prematurely before the /ACK was asserted, then a new microprocessor cycle can start after one clock cycle. NOTE: Asserting both read and write lines together while the chip select is asserted (/RD = 0, /WR = 0, and / CS = 0) will cause the device to operate in an undefined manner.
SE_CLK /CS Twcy /RD /WR Tqk Tvk Tvk Tvdk /ACK Thc Thc Thc Thc Thc Thc Tqk
Tqd DATA(7:0) Tva Tva ADD(7:0)
Tvd
Thd
Tha
Tva
Tha
Figure 37. Microprocessor Timing
Table 27. Symbol Parameter /ACK valid after /CS, /RD, or / WR, whichever is low last SE_CLK-to-output delay
Microprocessor Timing Conditions Min 2 1 Max 118 10 Unit SE_CLK cycles ns
Tvk Tqk
/ACK /ACK
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Table 27. Symbol Parameter SE_CLK-to-output delay Data valid prior to /ACK assertion Data valid after /CS or /WR, whichever is low last Address valid after /CS, /RD, or /WR, whichever is low last Address hold after /ACK assertion Data hold after /ACK assertion for write cycle Hold time after /CS, /RD, or / WR, whichever is high first Wait time between two consecutive cycles
Issue 3
Microprocessor Timing (Continued) Conditions DATA(7:0) DATA(7:0) DATA(7:0) ADD(7:0) ADD(7:0) DATA(7:0) /ACK, DATA(7:0) /CS, /RD, /WR 0 0 1.2 1 Min 1 SE_CLK cycle - 10.3 Max 13.5 ns ns SE_CLK cycle SE_CLK cycles ns ns ns SE_CLK cycles Unit
Tqd Tvdk Tvd Tva Tha Thd Thc Twcy
1 1
8.2
RAM Timing
The RAM interface is a synchronous interface, with respect to the RAM_CLK. Each read or write operation lasts for at least two clock cycles because of the internal 32-bit data bus. Recall that the RAM_DATA bus is covered by one bit of parity, named RAM_PARITY; this parity bit signal follows the same timing constraints and timing guarantees as the rest of the data bus.
Tck SE_CLK Tsd RAM_CLK Tq /RAM_WR Tq /RAM_OE Tqa RAM_ADD Tq Tqa Thd
RAM_DATA
Figure 38. RAM Interface Table 28. Parameter SE_CLK to RAM_CLK RAM_CLK RAM Interface Timing Conditions 0.5 Min 2.5 Max Unit ns
Symbol
Tck
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Table 28. Parameter RAM_CLK-to-output delay RAM_CLK setup time RAM_CLK hold time RAM_CLK-to-output delay
Issue 3
RAM Interface Timing (Continued) Conditions /RAM_WR, /RAM_OE, RAM_DATA RAM_DATA RAM_DATA RAM_ADD 1.5 5.2 0 1.5 Min 9 Max Unit ns ns ns ns
Symbol
Tq
Tsd Thd Tqa
10
8.3
QSE Interface Timing
Figure 39 shows the bit-level timing for the QSE.
Tctsu Tsesu SE_CLK Tseho SE_D_IN(31:0, 3:0), BP_ACK_IN(31:0) Tseq SE_D_OUT(31:0,3:0), BP_ACK_OUT(31:0) Tctho CELL_START, CELL_24_START Tseq SE_SOC_OUT(7:0) Fseclk
Figure 39. QSE Bit-Level Timing Parameter Frequency of SE_CLK Control signal setup Control signal hold Output delay from SE_CLK SE_CLK CELL_START, CELL_24_START CELL_START, CELL_24_START SE_D_OUT (15 pF), BP_ACK_OUT(31:0), SE_SOC_OUT(7:0)b SE_D_OUT(0,3:0) and SE_SOC_OUT SE_D_OUT(1,3:0) and SE_SOC_OUT SE_D_OUT(2,3:0) and SE_SOC_OUT SE_D_OUT(3,3:0) and SE_SOC_OUT SE_D_IN(0,3:0) and SE_SOC_IN(0) SE_D_IN(1,3:0) and SE_SOC_IN(1) SE_D_IN(2,3:0) and SE_SOC_IN(2) SE_D_IN(3,3:0) and SE_SOC_IN(3) Signals Min 35a 8.0 0 1 6 Max 66 Unit MHz ns ns ns
Symbol
Fseclk Tctsu Tctho Tseq
Output delay skew *
1.9
ns
Input delay skew *
3.5
ns
*
When the phase aligners are turned on, Tsesu and Tseho are no longer defined. However, the maximum input and output skew and jitter on these signals with respect to the SE_SOC_IN is constrained to specification listed in this table.
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a. For the phase aligners to lock. b. In real applications the output skew will be lower than 1.9ns. The reason for this is as follows. When all pins are equally loaded, SE_SOC_OUT is faster than all the SE_D_OUTs by (upto) 1.9ns. However, in real applications SE_SOC_OUT will have fan-out of four, and hence will be loaded four times as much as the other pins. This will slow down SE_SOC_OUT and hence lower the output skew. Miscellaneous Timing
8.4
Timing for the CTRL_IN, STAT_OUT, TEST_MODE, IDDTN and DEBUG(1:0) signals is shown in Table 29.
Table 29. CTRL_IN, STAT_OUT, TEST_MODE and DEBUG Timing Parameter Control signal setup Control signal setup Control signal setup Control signal setup Control signal hold Control signal hold Control signal hold Control signal hold Output delay from SE_CLK Output delay from SE_CLK Signals STAT_OUT (when it behaves as i/p) CTRL_IN TEST_MODE IDDTN STAT_OUT (when it behaves as i/p) CTRL_IN TEST_MODE IDDTN STAT_OUT (when it behaves as o/p) DEBUG(1,0), Min 4 4 10 10 0 0 10 10 1 1.5 10 14 Max Unit ns ns ns ns ns ns ns ns ns ns
Symbol
Tdasu Tdasu Tdaho Tdaho Tdaho Tdaho Tdaho Tdaho Tdaq Tdeq
Figure 40 shows the reset pin (RESET) timing. The RESET signal must be asserted for a minimum time (Tres) to be properly processed internal to the QSE. The QSE remains in reset while RESET is asserted, and starts performing normally after Trstproc.
Trstproc SE_CLK Tres RESET CELL_START(i)
Figure 40. Reset Timing Symbol Parameter Reset assertion time Reset processing time Signals RESET RESET Min 10 2 3 Max Unit SE_CLK periods SE_CLK periods
Tres
Trstproc
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NOTE: RESET assertion and deassertion is asynchronous to the clock.
Timing information for the SOC, BP, and ACK is given in Table 30.
Table 30. Parameter SOC valid window Valid window when BP is accepted by QSE Valid window when BP is generated by QSE Valid window when ACK is accepted by QSE Min Local_CELL_START - 8 SE_SOC_OUT + 0 Valid Window Timing Max Local_CELL_START Local_CELL_START + 60 Unit SE_CLK periods SE_CLK periods
Symbol
Vsoc
Vbprec
Vbpgen
Local_CELL_START + 15 (But in early BP mode: Local CELL_START + 0 See "BP_CONTROL_REGISTER" on page 109) SE_SOC_OUT + 0
Local_CELL_START + 35 (But in early BP mode: Local_CELL_START + 15 See"BP_CONTROL_REGISTER" on page 109) (Next cell time's) Local_CELL_START - 8
SE_CLK periods
Vack
SE_CLK periods
Figure 41 shows the timing for the JTAG port. The /SCAN_TRST signal is asynchronous to SCAN_TCK.
Tjres SCAN_TRST(i) Tjsu Tjsu Tjh Tjh
Tch SCAN_TCK(i) SCAN_TMS(i) SCAN_TDI(i) Tqj SCAN_TDO(o)
Tcl
Tqj
Figure 41. JTAG Timing Parameter SCAN_TCK frequency SCAN_TCK high 40 Signals Min Max 10 Unit MHz ns
Symbol
Tch
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Symbol
Parameter SCAN_TCK low SCAN_TCK hold time SCAN_TCK setup time /SCAN_TRST low SCAN_TCK-to-output delay /SCAN_TRST-to-output delay SCAN_TDO
Signals
Min 40
Max
Unit ns ns ns ns
Tcl
Tjh
SCAN_TMS, SCAN_TDI SCAN_TMS, SCAN_TDI
20 20 40 20
Tjsu Tqj
Tjres
ns
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9
MICROPROCESSOR PORTS
Microprocessor Ports Summary
9.1
NOTES: * * * * * * All read/write port bits marked "Not used" must be written with the value 0 to maintain software compatibility with future versions. All port bits marked "Reserved" should not be written. Software modifications to these locations after setup may cause incorrect operation. For 16-bit registers at addresses X and (X+1), bit 15 is address X bit 7 and bit 0 is address (X+1) bit 0. For 32-bit registers at addresses X to (X+3), bit 31 is address X bit 7 and bit 0 is address (X+3) bit 0. For example, the INPUT_PORT_ENABLE register. For 128-bit registers at addresses X to (X+Fh), nibble 31 is address X bits 7 to 4 and nibble 0 is address (X+Fh) bits 3 to 0. For example, the INPUT_MARKED_CELLS_COUNT register. Registers marked with a "t" should only be modified while the chip is in software reset.
Table 31. Microprocessor Ports Summary Name Read or Write Chip Control/Status Registers REVISION CHIP_MODE MULTICAST_GROUP_INDEX MULTICAST_GROUP_VECTOR MULTICAST_GROUP_OP UC/MC_FAIRNESS_REGISTER EXTENDED_CHIP_MODE MULTICAST_GROUP_INDEX_MSB RESERVED R R/Wt R/W R/W R/W R/W R/Wt R/W -- Port Control/Status Registers INPUT_PORT_ENABLE OUTPUT_PORT_ENABLE INPUT_MARKED_CELLS_COUNT OUTPUT_MARKED_CELLS_COUNT PARITY_ERROR_PRESENT PARITY_ERROR_LATCH PARITY_ERROR_INT_MASK R/W R/W R R R R R/W Enable input ports and associated interrupts. Enable output ports and associated interrupts. Count of marked cells arriving at inputs. Count of marked cells leaving at outputs. Parity error status on inputs during the last cell time. Indicates if any parity errors have occurred since the last read. Enables/disables interrupt due to parity error. Contains the device revision number (namely, 01h). Assorted chip-configuration bits. Multicast group to be modified or read. Set of destinations comprising the multicast group. Operation to be performed. Unicast/Multicast behavior for cells of the same priority. Extended chip mode Highest byte of Multicast group to be modified or read. Description
Address (in Hex)
0 1
2-3 4-7 8
9-A B C
D-F
10-13 14-17 18-27 28-37
38-3B
3C-3F 40-43
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Table 31. Microprocessor Ports Summary (Continued) Name SE_INPUT_PORT_FAIL_PRESENT Read or Write R Description Indicates absence of special pattern on SOC or invalid cell present code on data lines or invalid idle cell code on data lines during the last cell time. Indicates if an SE_INPUT_PORT_FAIL has occurred since the last read. Indicates absence of special coding on BP_ACK_IN line on output ports during the last cell time. Indicates if a BP_ACK_FAIL has occurred since the last read. Indicates absence of back pressure on BP_ACK_IN line on output ports during the last cell time. Indicates if a BP_REMOTE_FAIL condition has occurred since the last read.
Address (in Hex) 44-47
48-4B
SE_INPUT_PORT_FAIL_LATCH BP_ACK_FAIL_PRESENT BP_ACK_FAIL_LATCH BP_REMOTE_FAIL_PRESENT BP_REMOTE_FAIL_LATCH RESERVED
R R R R R --
4C-4F 50-53 54-57
58-5B
5C-7F
Switch Control/Status Registers CONTROL_REGISTER INTERRUPT_STATUS_REGISTER MULTICAST_AGGREGATE_OUTPU T_MODE UNICAST_AGGREGATE_OUTPUT_ MODE SWITCH_FABRIC_ROW SWITCH_FABRIC_COLUMN CELL_START_OFFSET BP_CONTROL_REGISTER ACK_PAYLOAD R/Wt R R/Wt R/Wt R/Wt R/Wt R/Wt R/Wt R/W Various switch parameters. Identifies if an interrupt condition is present. Aggregate mode for multicast cells. Aggregate mode for unicast cells. Row number in switch fabric. Column number in switch fabric. Offset between internal and external CELL_START signals. Control backpressure functionality. Payload for ACK packet when ACK needs to be generated by the QSE for parity fail and regular congestion. Payload for ACK packet when ACK needs to be generated by the QSE because the entire gang is dead. Extended switch control register.
80 81 82
83
84 85 86 87 88
89
GANG_DEAD_ACK EXTENDED_SWITCH_MODE RESERVED
R/W Rt --
8A
8B-EF
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9.2 Note on Error Detection and Reporting The QSE detects six classes of errors and each error in every class is reported using two bits: * * Error_present: There is an error at the present moment Error_latched: There was an error sometime in the past, between now and the last time this register was read.
Of these two bits, errors latched in the Error_latched registers can be further used to generate interrupts to the microprocessor. The six detected classes of errors fall into two categories: Category 1: Errors that can be associated with an input or output port. Errors in this category are only detected if the corresponding port is enabled. * Input port failed: This means that one of the SOC_IN or DATA_IN wires is stuck or glitchy. The error_present register is at address 44-47, and the error_latched register is at address 48-4B. You can stop checking for this error by turning off the appropriate input ports using the register at address 10-13. BpAck failed: This means that one of the BPACK_IN wires is stuck or glitchy. The error_present register is at address 4C-4F, and the error_latched register is at address 50-53. So you can stop checking for this error by turning off the appropriate output port using the register at address 14-17. Remote failure: This means that the downstream QSE did not sent a BP packet on some BPACK_IN wire during some cell-time. By implication, it means that one of the SOC_OUT or DATA_OUT wires is stuck or glitchy (to which the downstream QSE responds by withholding the BP packet). The error_present register is at address 54-57, and the error_latched register is at address 58-5B. You can stop checking for this error by turning off the appropriate output port using the register at address 14-17. Parity error in a cell. The error_present register is at address 38-3B, and the error_latched register is at address 3C-3F. You can stop checking for this error by turning off the appropriate input ports using the register at address 10-13. A separate set of registers at address 40-43 allow you to disable interrupts due to this error. You can also globally disable all parity checks on input ports using the CHIP_MODE register (bit 6).
*
*
*
Each of the above four classes of errors has a "summary" bit in the interrupt status register (ISR) at address 81. The summary bit for a class is set if any enabled error is latched in that class. An actual interrupt to the microprocessor (due to these classes of errors) will be generated if any of the four summary bits in the ISR are set and if the global interrupt mask is enabled. Category 2: Errors in this category are global to the entire chip. * CSTART is out of lock. The error_present register is at address 80 (bit 7), and the error_latched register is at address 8A (bit 0). You can turn off the interrupt from this error using the register at address 80 (bit 6). If this error is causing an interrupt, this is indicated by bit 4 of the ISR (address 81). Parity error in external MC connection RAM. There is no error_present register. The error_latched register is at address B(bit 6). You can turn off the parity check using the register at address B(bit 4) and you can disable interrupts due to this error using address B(bit 5). This error will cause an interrupt if it has been latched and if interrupts from this error have not been disabled using the register at address B (bit 5). Microprocessor Ports Bit Definitions
*
9.3
NOTE: The bits reset to 0b unless otherwise indicated.
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PMC-980616 9.3.1 REVISION
Issue 3
This register contains the device revision number. Address: 0h Type: Read Only Format: Refer to the following table.
Field (Bits) REVISION (7:0) Description Revision number of the QSE device. Revision numbers start at 0.
9.3.2
CHIP_MODE Address: 1h Type: Read/Write Format: Refer to the following table.
Field (Bits) ENABLE_STAT_PINS (7) PARITY_CHECK (6) /NO_DATA_OUT (5) /NO_DATA_IN (4) MULTICAST_MODE (3) 1 0 1 0 Description Enable StatOut and CtrlIn pin functionality StatOut behaves like No Data In, and Ctrl In behaves like No Data Out. Parity checks on cell header disabled. Normal operation.
Current value at the /NO_DATA_OUT pin. Current value at the /NO_DATA_IN pin. 1 0 1 0 External RAM present. No external RAM. Writing a one to this bit will put the chip is in hardware reset (except the processor interface, which remains untouched). Writing a zero to this bit will take the chip out of hardware reset.
CHIP_HARDWARE_RESET (2)
Upon pin-reset, this bit comes up as a one. A zero must be explicitly written to this bit before the chip can function normally. SWITCH_MODE (1) Reserved (1:0) 1 0 Double switch mode. Single switch mode.
Write with a 0 to maintain future software compatibility.
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Issue 3 MULTICAST_GROUP_INDEX_REGISTER Address: 2-3h Type: Read/Write Format: Refer to the following table.
Field (Bits) MC_ADD (15:0)
Description Multicast group index to be used by MULTICAST_GROUP_OP (refer to section "9.3.5 MULTICAST_GROUP_OP" on page 97). This register has bits 15 to 0 of the index. The MULTICAST_GROUP_INDEX_MSB register has the remaining.
9.3.4
MULTICAST_GROUP_VECTOR_REGISTER Address: 4-7h Type: Read/Write Format: Refer to the following table.
Field (Bits) MC_GROUP (31:0) Description Multicast Group Vector (MGV) data to be used by MULTICAST_GROUP_OP (refer to section "9.3.5 MULTICAST_GROUP_OP" on page 97). Address 45h bit 7 corresponds to the highest register bit, and 42h bit 0 corresponds to the lowest register bit. Depending on the multicast gang mode, only certain bits are active, and the active bits are as follows: Gang 1 mask FFFFFFFFh Gang 2 mask 0F0F0F0Fh Gang 4 mask 03030303h 1 Enables the transmission of a cell on the multicast group corresponding to the active bit number. 0 Disables the transmission of a cell on the multicast group corresponding to the active bit number.
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PMC-980616 9.3.5 MULTICAST_GROUP_OP Address: 8h Type: Read/Write Format: Refer to the following table.
Field (Bits) Not used (7:2) INC_BIT (1)
Issue 3
Description Write with a 0 to maintain future software compatibility. Increment Bit. 1 Autoincrement MULTICAST_GROUP_INDEX_REGISTER (refer to section "9.3.3 MULTICAST_GROUP_INDEX_REGISTER" on page 96) after each operation. 0 Leave MULTICAST_GROUP_INDEX_REGISTER unchanged. Operation Bit. 1 Enables the write of MULTICAST_GROUP_VECTOR_REGISTER to the multicast group vector equal to the address referenced by MULTICAST_GROUP_INDEX_REGISTER. 0 Enables the read of MULTICAST_GROUP_VECTOR_REGISTER from the multicast group vector equal to the address referenced by MULTICAST_GROUP_INDEX_REGISTER.
OPERATION_BIT (0)
9.3.6
UC/MC_FAIRNESS_REGISTER Address: 9-Ah Type: Read/Write Format: Refer to the following table.
Field (Bits) UPPER PORTS (15:8) Description Suppose a UC cell and an MC cell of the same priority are contending for the same output port, where the output port number is between 31 and 16. If x bits are set, then the UC cell has an x/8 probability of winning over the MC cell. For example, if (any) 4 of the 8 bits are set, then a tie is broken randomly with a 50-50 chance of either one winning. If none of the bits are set, then MC always wins, and if all the bits are set then UC always wins. This register resets to 3Ah. Same as above, except this register controls output ports between 15 and 0. Another difference is that this register resets to A3h.
LOWER PORTS (7:0)
9.3.7
EXTENDED_CHIP_MODE Address: Bh Type: Read/Write
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Field (Bits) Not used (7) RAM_PARITY_ERR_SENSED (6) RAM_PARITY_INT_ENABLE (5) RAM_PARITY_ENABLE (4) Not used (3:1) SHORT_TAG_ENABLE
Issue 3
Description Write with a 0 to maintain future software compatibility. 1: A parity error was sensed in the external multicast RAM 0: No parity error was sensed or parity is not enabled 1: Enable interrupt on External Multicast Vector RAM parity error 0: No interrupt on RAM parity error 1: Enable parity checking for the external multicast vector RAM 0: Disable parity checking for the external multicast vector RAM Write with a 0 to maintain future software compatibility. 1: Rotate only 5 nibbles of the routing tag. 0: Rotate all 8 nibbles of the routing tag. When the QSE receives a unicast cell, it looks at the initial portion of the cell's routing tag, and interprets it to be the destination gang of the cell. Before sending the cell out on that destination, the QSE cyclically shifts the routing tag leftwards. The purpose of this shift is to move new bits into the initial portion of the routing tag, thus making the routing tag suitable for use by the next-stage QSE. The amount of the rotation is equal to (5 - UC output gang mode) bits. (For a discussion on UC output gang mode, see section "9.3.25 UNICAST_AGGREGATE_OUTPUT_MODE" on page 106.) If SHORT_TAG_ENABLE is set to 1, then only 5 nibbles are rotated. Hence, the last 3 nibbles are left untouched, and they could potentially be used by the traffic manager to send diagnostic information. The QRT currently does not *NOT* use these 3 nibbles for anything. Therefore, when the QSE is used in conjunction with the QRT, there is no advantage to short tags, and the SHORT_TAG_ENABLE bit may remain at the reset-default value of 0.
9.3.8
MULTICAST_GROUP_INDEX_MSB Address: Ch Type: Read/Write Format: Refer to the following table.
Field (Bits) MGI_MSB (1:0) Description Bits 17 and 16 of the multicast group index. Use along with the MULTICAST_GROUP_INDEX_REGISTER
9.3.9
INPUT_PORT_ENABLE Address: 10-13h
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PMC-980616 Type: Read/Write Format: Refer to the following table.
Field (Bits) (31:0)
Issue 3
Description Bit x: 1 Enable input port x. 0 Disable input port x and interrupts due to SE_INPUT_PORT_FAIL_PRESENT (refer to section "9.3.16 SE_INPUT_PORT_FAIL_PRESENT" on page 101).
9.3.10
OUTPUT_PORT_ENABLE Address: 14-17h Type: Read/Write Format: Refer to the following table.
Field (Bits) (31:0) Description Bit x: 1 Enable output port x. 0 Disable output port x and interrupts due to BP_ACK_FAIL_PRESENT (refer to section "9.3.18 BP_ACK_FAIL_PRESENT" on page 102) and BP_REMOTE_FAIL_PRESENT (refer to section "9.3.20 BP_REMOTE_FAIL_PRESENT" on page 103).
9.3.11
INPUT_MARKED_CELLS_COUNT Address: 18-27h Type: Read only Format: Refer to the following table.
Field (Bits) Nibble 31 - Nibble 0 Description Nibble x: Number of cells mod 16 on input port x that had Tag(9,1) set to 1. All marked cells that enter on that port will be counted, even if they are discarded later on due to other reasons (e.g. multicast cell with parity errored header, or a multicast cell sent in violation of back-pressure.)
9.3.12
OUTPUT_MARKED_CELLS_COUNT Address: 28-37h Type: Read only
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PMC-980616 Format: Refer to the following table.
Field (Bits) Nibble 31 - Nibble 0
Issue 3
Description Nibble x: Number of cells mod 16 on output port x that had Tag(9,1) set to 1.
9.3.13
PARITY_ERROR_PRESENT Address: 38-3Bh Type: Read only Format: Refer to the following table.
Field (Bits) (31:0) Description Indicates if a parity error was present on the input port data lines during the last cell time. Bit x: 1 Error detected on input port x. 0 No error on input port x.
9.3.14
PARITY_ERROR_LATCH Address: 3C-3Fh Type: Read only Format: Refer to the following table.
Field (Bits) (31:0) Description Indicates if a parity error occurred on an input port since the last time this register was read. Bit x: 1 Error detected on input port x. 0 No error on input port x. Reset to 0 on read.
9.3.15
PARITY_ERROR_INT_MASK Address: 40-43h Type: Read/Write Format: Refer to the following table.
Field (Bits) (31:0) Description Bit x: 1 Enable interrupt due to parity condition latched for input port x. 0 Disable interrupt due to parity condition latched for input port x.
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PMC-980616 9.3.16 SE_INPUT_PORT_FAIL_PRESENT Address: 44-47h Type: Read only Format: Refer to the following table.
Field (Bits) (31:0)
Issue 3
Description Bit x: 1 Indicates that one or more of the following conditions were true for input port x during the last cell time: - Special pattern on SE_SOC_IN is absent. - Presence of an invalid cell present code. - Presence of an invalid idle cell code. 0 Normal.
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Long Form Data Sheet
PMC-980616 9.3.17 SE_INPUT_PORT_FAIL_LATCH Address: 48-4Bh Type: Read only Format: Refer to the following table.
Field (Bits) (31:0)
Issue 3
Description Bit x: 1 An SE_INPUT_PORT_FAIL_PRESENT (refer to section "9.3.16 SE_INPUT_PORT_FAIL_PRESENT" on page 101) has occurred on input port x since the last time this register was read. 0 Normal. Reset to 0 on read.
9.3.18
BP_ACK_FAIL_PRESENT Address: 4C-4Fh Type: Read only Format: Refer to the following table.
Field (Bits) (31:0) Description Bit x: 1 Indicates absence of special pattern on the BP_ACK line for output x. 0 Normal
9.3.19
BP_ACK_FAIL_LATCH Address: 50-53h Type: Read only Format: Refer to the following table.
Field (Bits) (31:0) Description Bit x: 1 A BP_ACK_FAIL_PRESENT has occurred on output x since the last time this register was read. 0 Normal. Reset to 0 on read.
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PMC-980616 9.3.20 BP_REMOTE_FAIL_PRESENT Address: 54-57h Type: Read only Format: Refer to the following table.
Field (Bits) (31:0)
Issue 3
Description Bit x: 1 Indicates absence of back pressure on BP_ACK line for output x during last cell time. 0 Normal.
9.3.21
BP_REMOTE_FAIL_LATCH Address: 58-5Bh Type: Read only Format: Refer to the following table.
Field (Bits) (31:0) Description Bit x: 1 Indicates a BP_REMOTE_FAIL_PRESENT (refer to section "9.3.18 BP_ACK_FAIL_PRESENT" on page 102) has occurred on output x since the last time this register was read. 0 Normal. Reset to 0 on read.
9.3.22
CONTROL_REGISTER Address: 80h Type: Read/Write Format: Refer to the following table.
Field (Bits) Description 1 0 CELL_START is in lock. CELL_START is not in lock.
CELL_START_IN_LOCK (7)
This bit may be viewed as the complemented form of the error_present indicator CELL_START_OUT_OF_LOCK_PRESENT. The corresponding error_latched indicator may be found in section "9.3.32 EXTENDED_SWITCH_MODE" on page 110. For a general discussion on error_present and error_latched indicators, see section "9.2 Note on Error Detection and Reporting" on page 94. CELL_START_OUT_OF_LOCK_ INT_MASK (6) 1 0 Interrupt when CELL_START out of lock. No interrupt when CELL_START is out of lock.
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Field (Bits) Reserved (5) PHASE_ALIGNER_MODE (4)
Description Write with a 0 to maintain future software compatibility. 1 0 Phase aligner off. Phase aligner on.
This bit should remain cleared (i.e. 0) for normal operation. Reserved (3) Reserved (2) INT_ENABLE (1) Write with a 0 to maintain future software compatibility. Write with a 0 to maintain future software compatibility. 1 Global interrupt enabled. 0 Global interrupt disabled. The interrupt will remain asserted as long as this bit is set and at least one of the bits in the interrupt status register is set. Unfortunately, setting this bit to 0 does not disable interrupts due to ram parity-error and cstart out-of-lock. They need to be disabled separately. Ram parity-error interrupt may be disabled using bit 5 of "EXTENDED_CHIP_MODE" on page 97. Cstart out-of-lock interrupt may be disabled using bit 6 of "CONTROL_REGISTER" on page 103. 1 Writing a one to this bit will put the chip in software reset. This means that the processor interface will remain untouched, and the remaining blocks in the chip will be reset only some portion of their state (depending on the discretion of the designer). Writing a zero to this bit will take the chip out of software reset.
SW_RESET (0)
0
Upon pin-reset, this bit comes up as a one. A zero must be explicitly written to this bit before the chip can function normally.
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PMC-980616 9.3.23 INTERRUPT_STATUS_REGISTER Address: 81h Type: Read only Format: Refer to the following table.
Field (Bits) Not used (7:4) CSTART_OUT_OF_LOCK (4) PARITY_ERROR (3) INPUT_PORT_FAIL (2) BP_ACK_FAIL (1) BP_REMOTE_FAIL (0)
Issue 3
Description Driven with a 0. Mask on reads to maintain compatibility with future versions. CELL_START out-of-lock interrupt is enabled and CELL_START out-oflock latch is on. An input in which PARITY_ERROR_INT_MASK (refer to section "9.3.15 PARITY_ERROR_INT_MASK" on page 100) is enabled has a latched parity error. An enabled input has a latched SE_INPUT_PORT_FAIL_LATCH (refer to section "9.3.17 SE_INPUT_PORT_FAIL_LATCH" on page 102). An enabled output has a latched BP_ACK_FAIL_LATCH (refer to section "9.3.21 BP_REMOTE_FAIL_LATCH" on page 103). An enabled output has a latched BP_REMOTE_FAIL_LATCH (refer to section "9.3.21 BP_REMOTE_FAIL_LATCH" on page 103).
This register can be used to check status in polled mode even if interrupts are disabled in the CONTROL_REGISTER (refer to section "9.3.22 CONTROL_REGISTER" on page 103).
9.3.24
MULTICAST_AGGREGATE_OUTPUT_AND_INPUT_MODES Address: 82h Type: Read/Write Note: Also called multicast gang mode register Format: Refer to the following table.
Field (Bits) Not used (7) Description Write with a 0 to maintain future software compatibility.
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Field (Bits) MULTICAST_AGG_OUT (6:4)
Description Selects aggregate of N. That is, N consecutive outputs are treated as a single output by the switch for multicast traffic. (2:0) = 3 - 7 are invalid. (2:0) = 2, N = 4. (2:0) = 1, N = 2. (2:0) = 0, N = 1. Aggregate mode is also called "gang mode" in other parts of this document. Note: The unicast output gang mode (see section "9.3.25 UNICAST_AGGREGATE_OUTPUT_MODE" on page 106) must be set to a value greater than or equal to the multicast output gang mode.
Not used (3) MULTICAST_AGG_IN (2:0)
Write with a 0 to maintain future software compatibility. Selects aggregate of N. That is, N consecutive inputs are treated as a single input by the switch for multicast traffic. (2:0) = 3 - 7 are invalid. (2:0) = 2, N = 4. (2:0) = 1, N = 2. (2:0) = 0, N = 1. Aggregate mode is also called "gang mode" in other parts of this document.
9.3.25
UNICAST_AGGREGATE_OUTPUT_MODE Address: 83h Type: Read/Write Note: Also called unicast gang mode register
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PMC-980616 Format: Refer to the following table.
Field (Bits) UNICAST_AGG_OUT (2:0)
Issue 3
Description Selects aggregate of N. N consecutive outputs are treated as a single output by the switch for unicast traffic. (2:0) = 6 - 7 are invalid. (2:0) = 5 puts in the QSE in randomization mode. (2:0) = 4, N = 16. (2:0) = 3, N = 8. (2:0) = 2, N = 4. (2:0) = 1, N = 2. (2:0) = 0, N = 1. Note that this register determines whether the QSE is in randomization mode or switching mode: when bits (2:0) have the value 5 then the QSE is in randomization mode, and when bits (2:0) have a value between 4 and 0 then the QSE is in switching mode. Thus, for example, in a 3-stage switch fabric, all the QSEs in the 1st stage should have UNICAST_AGG_OUT set to 5, and all the QSEs in the 2nd and 3rd stage should have UNICAST_AGG_OUT set to values between 4 and 0. The rationale behind this encoding is that randomization mode may be viewed as switching mode with N = 32, because in randomization mode a unicast cell is "switched" to any of the 32 output ports. Note that "aggregate mode" is also called "gang mode" in other parts of this document. Note: The multicast output gang mode (see section "9.3.24 MULTICAST_AGGREGATE_OUTPUT_AND_INPUT_MODES" on page 105) must be set to a value less than or equal to the unicast output gang mode
9.3.26
SWITCH_FABRIC_ROW Address: 84h Type: Read/Write
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PMC-980616 Format: Refer to the following table.
Field (Bits) (7:0)
Issue 3
Description R x PG where: R= the Row number in the switching fabric for this switch element. The numbering of rows starts from 0. PG = the Physical Gang of the QSE, which is defined as the number of output ports that physically connect this QSE to a chip (QSE or QRT) in the next stage. Note that PG can have a value of 1,2,4,8, or 16 if the next stage consists of QSEs, and it can have a value of 1,2, or 4 if the next stage consists of QRTs. If the value (R x PG ) exceeds 8 bit, the upper bits (i.e. MSBs) should be truncated, to leave the lower 8 bits in the SWITCH_FABRIC_ROW register.
9.3.27
SWITCH_FABRIC_COLUMN Address: 85h Type: Read/Write Format: Refer to the following table.
Field (Bits) (7:0) Description C + 16P where: C = the Column number in the switching fabric for this switch element. The numbering of columns starts from 0. P = the plane number if there are multiple parallel switch planes. The numbering of planes also starts from 0.
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PMC-980616 9.3.28 CELL_START_OFFSET Address: 86h Type: Read/Write Format: Refer to the following table.
Field (Bits) Not used (7) (6:0)
Issue 3
Description Write with a 0 to maintain future software compatibility. Offset between (external) CELL_START and Local CELL_START (NOTE:
The CSTART offset must only be changed when the device is in software reset.) Legal values for this register are between 0 and 117.
9.3.29
BP_CONTROL_REGISTER Address: 87h Type: Read/Write Format: Refer to the following table. Note: The BP_CONTROL_REGISTER is typically used for fine-tuning multicast performance. For initial system bring-up, this register may be left at the power-up default value.
Field (Bits) Not used (7:4) GLOBAL_LIMIT_2 (3) GLOBAL_LIMIT_1 (2) PER_PORT_LIMIT (1) EARLY_BP (0) Description Write with a 0 to maintain future software compatibility. If 1, second port threshold is off. If 1, first port threshold is off. 1 0 1 0 Each port allowed to have a maximum of 4 cells pending. Each port allowed to have a maximum of 3 cells pending. Early (hence conservative) backpressure. Optimal backpressure.
9.3.30
ACK_PAYLOAD Address: 88h Type: Read/Write Format: Refer to the following table.
Field (Bits) PARITY_NACK (7:4) Description ACK Payload for Parity Error Cells. Reset to 8h (Default is ONACK).
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Field (Bits) CONGESTION_NACK (3:0)
Description ACK Payload for cells dropped due to congestion. Reset to 4h (Default is MNACK).
9.3.31
GANG_DEAD_ACK_PAYLOAD Address: 89h Type: Read/Write Format: Refer to the following table.
Field (Bits) Not used (7:4) Description Write with a 0 to maintain future software compatibility. ACK Payload for cells dropped when an entire gang is disabled. A gang is defined as a set of consecutive outputs that is treated as a single output by the switch for unicast traffic (see "UNICAST_AGGREGATE_OUTPUT_MODE" on page 106 ). This field resets to Ch (which is interpreted by the QRT as an ACK).
GANG_DEAD_NACK (3:0)
9.3.32
EXTENDED_SWITCH_MODE Address: 8Ah Type: Read Format: Refer to the following table.
Field (Bits) Description
LATCHED_CELL_START_OUT_ Cleared on read. Set anytime cstart goes out of lock. OF_LOCK (0)
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10
JTAG
10.1 JTAG Support The QRT supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO, used to control the TAP controller and the boundary scan registers. The TRSTB input is the active low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below.
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
Figure 42. Boundary Scan Architecture The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a single bit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code.
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The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register place in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs. 10.2 TAP Controller The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.
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TRSTB=0 Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 0 1 Exit1-IR 0 Pause-IR 1 0 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
Figure 43. TAP Controller Finite State Machine
10.2.1
Test-Logic-Reset:
The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the
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instruction register is set to the IDCODE instruction. Run-Test-Idle:
10.2.2
The run test/idle state is used to execute tests. Capture-DR:
10.2.3
The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR:
10.2.4
The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR:
10.2.5
The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR:
10.2.6
The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR:
10.2.7
The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-IR:
10.2.8
The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. The TDO output is enabled during states Shift-DR and Shift-IR. Otherwise, it is tri-stated.
10.3 Boundary Scan Instructions The following is a description of the standard instructions. Each instruction selects an serial test data register path between input, TDI, and output, TDO. 10.3.1 BYPASS
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST
10.3.2
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is place between input TDI and output TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state.
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PMC-980616 10.3.3 SAMPLE
Issue 3
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. IDCODE
10.3.4
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. STCTEST
10.3.5
The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out on output TDO using the Shift-DR state. Boundary Scan Pin Order
Table 32. Boundary Scan Pin order Pin # Pin name Pin Type
10.4
Order #
0 1
HIZ HIZ HIZ HIZ HIZ HIZ HIZ HIZ HIZ HIZ G6 D3 J6 C2 K6 K6 E2 SCAN_ENN OEN CELL_START CELL_24_START STAT_OUT_NDI STAT_OUT_NDI CTRL_IN_NDO
output enable output enable output enable output enable output enable output enable output enable output enable output enable output enable clock clock clock clock output3 input clock
2 3 4 5 6 7 8 9
10 11
12 13 14 15 16
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17
F3 C1 D2 H3 J5 K5 K4 J4 G2 D1 L5 J3 M6 N6 F1 K3 H2 M5 L4 H1 M3 J2 N4 G1 K1 L2 N3 P6 N5
SE_D_IN16.0 SE_D_IN16.1 SE_D_IN16.2 SE_D_IN16.3 SE_SOC_IN16 SE_D_IN17.0 SE_D_IN17.1 SE_D_IN17.2 SE_D_IN17.3 SE_SOC_IN17 SE_D_IN18.0 SE_D_IN18.1 SE_D_IN18.2 SE_D_IN18.3 SE_SOC_IN18 SE_D_IN19.0 SE_D_IN19.1 SE_D_IN19.2 SE_D_IN19.3 SE_SOC_IN19 SE_D_IN20.0 SE_D_IN20.1 SE_D_IN20.2 SE_D_IN20.3 SE_SOC_IN20 SE_D_IN21.0 SE_D_IN21.1 SE_D_IN21.2 SE_D_IN21.3
clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock
18
19 20 21
22 23 24
25 26
27
28 29 30
31 32 33
34 35 36
37 38 39
40 41
42
43 44 45
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46
R6 M2 L1 P5 N2 R5 P4 R4 P3 P1 M1 R2 T2 R1 U1 T1 T4 W1 T5 V2 U3 Y1 U4 T6 U5 U6 V3 W2 AA1
SE_SOC_IN21 SE_D_IN22.0 SE_D_IN22.1 SE_D_IN22.2 SE_D_IN22.3 SE_SOC_IN22 SE_D_IN23.0 SE_D_IN23.1 SE_D_IN23.2 SE_D_IN23.3 SE_SOC_IN23 SE_D_IN24.0 SE_D_IN24.1 SE_D_IN24.2 SE_D_IN24.3 SE_SOC_IN24 SE_D_IN25.0 SE_D_IN25.1 SE_D_IN25.2 SE_D_IN25.3 SE_SOC_IN25 SE_D_IN26.0 SE_D_IN26.1 SE_D_IN26.2 SE_D_IN26.3 SE_SOC_IN26 SE_D_IN27.0 SE_D_IN27.1 SE_D_IN27.2
clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock
47
48 49 50
51 52
53
54 55
56
57 58
59
60 61 62
63 64 65
66
67 68
69 70 71
72 73 74
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75 76
V5 V4 Y2 W3 AC1 AD1 W5 AB2 AA3 Y4 V6 W6 AC2 Y5 AE1 AD2 AB3 AA4 AA5 AG1 AC3 AB4 AH1 AB5 AF2 AA6 AG2 AB6 AE3
SE_D_IN27.3 SE_SOC_IN27 SE_D_IN28.0 SE_D_IN28.1 SE_D_IN28.2 SE_D_IN28.3 SE_SOC_IN28 SE_D_IN29.0 SE_D_IN29.1 SE_D_IN29.2 SE_D_IN29.3 SE_SOC_IN29 SE_D_IN30.0 SE_D_IN30.1 SE_D_IN30.2 SE_D_IN30.3 SE_SOC_IN30 SE_D_IN31.0 SE_D_IN31.1 SE_D_IN31.2 SE_D_IN31.3 SE_SOC_IN31 RAM_ADD.17 BP_ACK_OUT.0 BP_ACK_OUT.1 BP_ACK_OUT.2 BP_ACK_OUT.3 BP_ACK_OUT.4 BP_ACK_OUT.5
clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock output3 output3 output3 output3 output3 output3 output3
77 78
79
80 81
82
83 84 85
86 87 88
89 90
91
92 93 94
95 96
97
98 99
100
101 102
103
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104
AC5 AH2 AD4 AD6 AG3 AE4 AD5 AE5 AF4 AJ1 AK2 AG5 AF6 AF7 AG6 AH4 AE7 AG7 AJ3 AF8 AH6 AE9 AJ4 AE10 AJ5 AF9 AK3 AG9 AH8
BP_ACK_OUT.6 BP_ACK_OUT.7 BP_ACK_OUT.8 BP_ACK_OUT.9 BP_ACK_OUT.10 BP_ACK_OUT.11 BP_ACK_OUT.12 BP_ACK_OUT.13 BP_ACK_OUT.14 BP_ACK_OUT.15 BP_ACK_OUT.16 BP_ACK_OUT.17 BP_ACK_OUT.18 BP_ACK_OUT.19 BP_ACK_OUT.20 BP_ACK_OUT.21 BP_ACK_OUT.22 BP_ACK_OUT.23 BP_ACK_OUT.24 BP_ACK_OUT.25 BP_ACK_OUT.26 BP_ACK_OUT.27 BP_ACK_OUT.28 BP_ACK_OUT.29 BP_ACK_OUT.30 BP_ACK_OUT.31 ADD.0 ADD.1 ADD.2
output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 clock clock clock
105
106 107
108
109 110 111
112 113 114
115 116 117
118 119
120
121 122
123
124 125
126
127 128
129
130 131 132
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133 134
AK4 AF10 AG10 AH9 AJ7 AK6 AK6 AF11 AF11 AJ8 AJ8 AE12 AE12 AE13 AE13 AG11 AG11 AH10 AH10 AJ9 AJ9 AF12 AK7 AK8 AH12 AJ11 AG13 AF13 AK10
ADD.3 ADD.4 ADD.5 ADD.6 ADD.7 DATA.0 DATA.0 DATA.1 DATA.1 DATA.2 DATA.2 DATA.3 DATA.3 DATA.4 DATA.4 DATA.5 DATA.5 DATA.6 DATA.6 DATA.7 DATA.7 RAM_ADD.18 CSN RDN WRN ACKN INTRN RESET SE_D_OUT31.0
clock clock clock clock clock output3 input output3 input output3 input output3 input output3 input output3 input output3 input output3 input output3 clock clock clock output3 output3 clock output3
135 136 137
138 139 140
141 142 143
144 145
146
147
148 149
150 151 152
153 154 155
156
157 158
159
160 161
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162 163
AJ12 AH13 AE14 AF14 AE15 AG14 AK11 AH14 AJ13 AF15 AK12 AG15 AK15 AK14 AK16 AJ15 AK19 AK17 AH17 AG16 AG17 AF16 AJ18 AF17 AK20 AJ19 AE16 AF18 AE17
SE_D_OUT31.1 SE_D_OUT31.2 SE_D_OUT31.3 SE_D_OUT30.0 SE_D_OUT30.1 SE_D_OUT30.2 SE_D_OUT30.3 SE_D_OUT29.0 SE_D_OUT29.1 SE_D_OUT29.2 SE_D_OUT29.3 SE_D_OUT28.0 SE_D_OUT28.1 SE_D_OUT28.2 SE_D_OUT28.3 SE_SOC_OUT7 SE_D_OUT27.0 SE_D_OUT27.1 SE_D_OUT27.2 SE_D_OUT27.3 SE_D_OUT26.0 SE_D_OUT26.1 SE_D_OUT26.2 SE_D_OUT26.3 SE_D_OUT25.0 SE_D_OUT25.1 SE_D_OUT25.2 SE_D_OUT25.3 SE_D_OUT24.0
output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3
164 165 166
167 168 169
170 171 172
173 174 175
176 177 178
179 180 181
182 183 184
185 186 187
188 189 190
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191 192
AH18 AJ20 AK21 AK24 AG18 AJ22 AH19 AK23 AG20 AF19 AJ23 AH21 AK25 AE18 AE19 AH22 AF20 AK27 AJ24 AG22 AG21 AF21 AF22 AH23 AJ27 AK28 AH25 AJ26 AE21
SE_D_OUT24.1 SE_D_OUT24.2 SE_D_OUT24.3 SE_SOC_OUT6 SE_D_OUT23.0 SE_D_OUT23.1 SE_D_OUT23.2 SE_D_OUT23.3 SE_D_OUT22.0 SE_D_OUT22.1 SE_D_OUT22.2 SE_D_OUT22.3 SE_D_OUT21.0 SE_D_OUT21.1 SE_D_OUT21.2 SE_D_OUT21.3 SE_D_OUT20.0 SE_D_OUT20.1 SE_D_OUT20.2 SE_D_OUT20.3 SE_SOC_OUT5 SE_D_OUT19.0 SE_D_OUT19.1 SE_D_OUT19.2 SE_D_OUT19.3 SE_D_OUT18.0 SE_D_OUT18.1 SE_D_OUT18.2 SE_D_OUT18.3
output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3
193 194 195
196 197 198
199 200 201
202 203 204
205 206 207
208 209 210
211
212 213
214 215 216
217 218 219
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
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220 221
AJ28 AE22 AH27 AF23 AF24 AG24 AE24 AG26 AG25 AF25 AK29 AE26 AD26 AE27 AG28 AD25 AD27 AH29 AC26 AE28 AB25 AG29 AA25 AF29 AB26 AH30 AB27 AC28 AG30
SE_D_OUT17.0 SE_D_OUT17.1 SE_D_OUT17.2 SE_D_OUT17.3 SE_D_OUT16.0 SE_D_OUT16.1 SE_D_OUT16.2 SE_D_OUT16.3 SE_SOC_OUT4 SE_CLK_BYPASS SE_D_OUT15.0 SE_D_OUT15.1 SE_D_OUT15.2 SE_D_OUT15.3 SE_D_OUT14.0 SE_D_OUT14.1 SE_D_OUT14.2 SE_D_OUT14.3 SE_D_OUT13.0 SE_D_OUT13.1 SE_D_OUT13.2 SE_D_OUT13.3 SE_D_OUT12.0 SE_D_OUT12.1 SE_D_OUT12.2 SE_D_OUT12.3 SE_SOC_OUT3 SE_D_OUT11.0 SE_D_OUT11.1
output3 output3 output3 output3 output3 output3 output3 output3 output3 clock output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3
222 223 224
225 226 227
228 229
230
231 232 233
234 235 236
237 238
239
240
241 242
243 244
245
246 247
248
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
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249 250
AA26 AA27 AB28 AD29 AE30 Y26 AC29 W25 V25 Y27 AA28 AB29 W26 AD30 AC30 W28 Y29 V27 V26 AA30 W29 V28 U25 U26 T25 U27 Y30 U28 V29
SE_D_OUT11.2 SE_D_OUT11.3 SE_D_OUT10.0 SE_D_OUT10.1 SE_D_OUT10.2 SE_D_OUT10.3 SE_D_OUT09.0 SE_D_OUT09.1 SE_D_OUT09.2 SE_D_OUT09.3 SE_D_OUT08.0 SE_D_OUT08.1 SE_D_OUT08.2 SE_D_OUT08.3 SE_SOC_OUT2 SE_D_OUT07.0 SE_D_OUT07.1 SE_D_OUT07.2 SE_D_OUT07.3 SE_D_OUT06.0 SE_D_OUT06.1 SE_D_OUT06.2 SE_D_OUT06.3 SE_D_OUT05.0 SE_D_OUT05.1 SE_D_OUT05.2 SE_D_OUT05.3 SE_D_OUT04.0 SE_D_OUT04.1
output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3
251
252 253
254 255 256
257 258
259
260 261
262
263 264 265
266 267
268
269 270 271
272 273 274
275 276 277
124
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PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
278 279
T26 W30 T27 T30 U30 R30 T29 R29 M30 P30 P28 R27 P27 R26 N29 P26 L30 M29 R25 N26 P25 L29 K30 G30 N27 J29 M28 H30 L27
SE_D_OUT04.2 SE_D_OUT04.3 SE_SOC_OUT1 SE_D_OUT03.0 SE_D_OUT03.1 SE_D_OUT03.2 SE_D_OUT03.3 SE_D_OUT02.0 SE_D_OUT02.1 SE_D_OUT02.2 SE_D_OUT02.3 SE_D_OUT01.0 SE_D_OUT01.1 SE_D_OUT01.2 SE_D_OUT01.3 SE_D_OUT00.0 SE_D_OUT00.1 SE_D_OUT00.2 SE_D_OUT00.3 SE_SOC_OUT0 PLL_BYPASS_N BP_ACK_IN.0 BP_ACK_IN.1 BP_ACK_IN.2 BP_ACK_IN.3 BP_ACK_IN.4 BP_ACK_IN.5 BP_ACK_IN.6 BP_ACK_IN.7
output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 clock clock clock clock clock clock clock clock clock
280 281 282
283 284
285
286 287 288
289 290
291
292 293 294
295 296 297
298
299 300
301 302 303
304 305 306
125
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PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
307 308
M26 H29 K28 F30 N25 M25 J28 L26 D30 G29 J27 K27 K26 J26 H28 D29 C30 F28 E29 K25 C29 J25 D28 H26 G26 G27 G25 E27 F27
BP_ACK_IN.8 BP_ACK_IN.9 BP_ACK_IN.10 BP_ACK_IN.11 BP_ACK_IN.12 BP_ACK_IN.13 BP_ACK_IN.14 BP_ACK_IN.15 BP_ACK_IN.16 BP_ACK_IN.17 BP_ACK_IN.18 BP_ACK_IN.19 BP_ACK_IN.20 BP_ACK_IN.21 BP_ACK_IN.22 BP_ACK_IN.23 BP_ACK_IN.24 BP_ACK_IN.25 BP_ACK_IN.26 BP_ACK_IN.27 BP_ACK_IN.28 BP_ACK_IN.29 BP_ACK_IN.30 BP_ACK_IN.31 RAM_ADD.0 RAM_ADD.1 RAM_ADD.2 RAM_ADD.3 RAM_ADD.4
clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock output3 output3 output3 output3 output3
309
310 311
312 313 314
315 316 317
318 319 320
321 322
323
324 325 326
327 328 329
330
331 332
333 334 335
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PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
336
F26 B30 A29 E25 D25 D26 F24 D24 E24 E23 C27 F22 F22 B28 B28 F21 F21 B26 B26 C25 C25 A28 A28 B27 B27 C23 C23 E22 E22
RAM_ADD.5 RAM_ADD.6 RAM_ADD.7 RAM_ADD.8 RAM_ADD.9 RAM_ADD.10 RAM_ADD.11 RAM_ADD.12 RAM_ADD.13 RAM_ADD.14 RAM_ADD.15 RAM_DATA.0 RAM_DATA.0 RAM_DATA.1 RAM_DATA.1 RAM_DATA.2 RAM_DATA.2 RAM_DATA.3 RAM_DATA.3 RAM_DATA.4 RAM_DATA.4 RAM_DATA.5 RAM_DATA.5 RAM_DATA.6 RAM_DATA.6 RAM_DATA.7 RAM_DATA.7 RAM_DATA.8 RAM_DATA.8
output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 input output3 input output3 input output3 input output3 input output3 input output3 input output3 input output3 input
337
338 339 340
341 342 343
344 345
346
347 348
349
350 351 352
353 354
355
356 357 358
359 360
361
362 363 364
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
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365 366
E21 E21 D21 D21 D22 D22 B24 B24 A27 A27 E20 E20 C22 C22 F19 F18 F18 A25 C21 B23 E19 D20 A23 C19 B22 D18 A24 A21 B20
RAM_DATA.9 RAM_DATA.9 RAM_DATA.10 RAM_DATA.10 RAM_DATA.11 RAM_DATA.11 RAM_DATA.12 RAM_DATA.12 RAM_DATA.13 RAM_DATA.13 RAM_DATA.14 RAM_DATA.14 RAM_DATA.15 RAM_DATA.15 RAM_ADD.16 RAM_PARITY RAM_PARITY RAM_WRN RAM_OEN RAM_CLK SE_D_IN00.0 SE_D_IN00.1 SE_D_IN00.2 SE_D_IN00.3 SE_SOC_IN00 SE_D_IN01.0 SE_D_IN01.1 SE_D_IN01.2 SE_D_IN01.3
output3 input output3 input output3 input output3 input output3 input output3 input output3 input output3 output3 input output3 output3 output3 clock clock clock clock clock clock clock clock clock
367 368 369
370 371
372
373 374 375
376 377
378
379 380 381
382 383
384
385 386 387
388 389 390
391 392
393
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PMC-Sierra, Inc.
PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
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Issue 3
394 395
C18 F17 E18 F16 B19 A20 E17 B18 E16 D17 D16 C17 A17 A19 B16 B15 A16 A14 A15 D15 A12 E15 B13 C14 A11 D14 F15 E14 F14
SE_SOC_IN01 SE_D_IN02.0 SE_D_IN02.1 SE_D_IN02.2 SE_D_IN02.3 SE_SOC_IN02 SE_D_IN03.0 SE_D_IN03.1 SE_D_IN03.2 SE_D_IN03.3 SE_SOC_IN03 SE_D_IN04.0 SE_D_IN04.1 SE_D_IN04.2 SE_D_IN04.3 SE_SOC_IN04 SE_D_IN05.0 SE_D_IN05.1 SE_D_IN05.2 SE_D_IN05.3 SE_SOC_IN05 SE_D_IN06.0 SE_D_IN06.1 SE_D_IN06.2 SE_D_IN06.3 SE_SOC_IN06 SE_D_IN07.0 SE_D_IN07.1 SE_D_IN07.2
clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock
396 397
398
399
400
401
402 403 404
405 406 407
408 409 410
411
412 413
414
415
416
417
418 419
420 421 422
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
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423
C13 B12 A10 E13 D13 B11 C12 A8 A7 E12 B9 C10 D11 F13 F12 B8 E11 A6 B7 C9 D10 E10 A4 C8 D9 A3 E9 B5 F10
SE_D_IN07.3 SE_SOC_IN07 SE_D_IN08.0 SE_D_IN08.1 SE_D_IN08.2 SE_D_IN08.3 SE_SOC_IN08 SE_D_IN09.0 SE_D_IN09.1 SE_D_IN09.2 SE_D_IN09.3 SE_SOC_IN09 SE_D_IN10.0 SE_D_IN10.1 SE_D_IN10.2 SE_D_IN10.3 SE_SOC_IN10 SE_D_IN11.0 SE_D_IN11.1 SE_D_IN11.2 SE_D_IN11.3 SE_SOC_IN11 SE_D_IN12.0 SE_D_IN12.1 SE_D_IN12.2 SE_D_IN12.3 SE_SOC_IN12 SE_D_IN13.0 SE_D_IN13.1
clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock clock
424
425 426 427
428 429
430
431 432
433
434
435 436
437
438 439
440
441
442
443
444 445
446 447 448
449
450 451
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
452 453
B4 F9 C6 E8 B3 D7 F7 C4 D6 E7 E6 D5 A2
SE_D_IN13.2 SE_D_IN13.3 SE_SOC_IN13 SE_D_IN14.0 SE_D_IN14.1 SE_D_IN14.2 SE_D_IN14.3 SE_SOC_IN14 SE_D_IN15.0 SE_D_IN15.1 SE_D_IN15.2 SE_D_IN15.3 SE_SOC_IN15
clock clock clock clock clock clock clock clock clock clock clock clock clock
454 455
456
457 458
459
460 461 462
463 464
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
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APPENDIX A NOMENCLATURE
A.1 Definitions
Transmit signals: all signals related to processing the data heading towards the optical/electrical layer. Receive signals: all signals related to processing the data heading towards the ATM layer. A.2 Numbers Hexadecimal numbers are followed by the suffix "h", for example: 1h, 2Ch. Binary numbers are followed by the suffix "b", for example: 00b. Decimal numbers appear without suffixes. Glossary of Abbreviations
Table 33. Standard Abbreviations Abbreviation ACK ATM CLP CMOS CPU EPBGA IRT JTAG MB MC MGI MGV MNACK MPV NACK ONACK ORT PG PHY Acknowledgment Asynchronous Transfer Mode Cell Loss Priority Complementary Metal Oxide Semiconductor Central Processing Unit Enhanced Plastic Ball Grid Array Input half of QRT Joint Test Access Group Mark Bit Multicast Multicast Group Index Multicast Group Vector Mid Switch Negative ACKnowledgment Multicast Port Vector Negative ACKnowledgment Output Negative ACKnowledgment Output half of QRT Physical Gang Physical Description
*
*
*
A.3
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
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Table 33. Standard Abbreviations (Continued) Abbreviation PIF PLL PTI QRT QSE RAM SF SOC SP SRAM SSRAM UTOPIA VC VCI Description General-purpose microprocessor interface Phase Locked Loop Payload Type Indicator PMC's ATM traffic management chip (PM73487) PMC's ATM switch fabric chip (PM73488) Random Access Memory Speedup Factor Start-Of-Cell Spare Bit Static Random Access Memory Synchronous Static Random Access Memory Universal Test and Operations PHY Interface for ATM Virtual Channel Virtual Channel Identifier
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
APPENDIX B REFERENCES
* * ATM Forum, ATM User-Network Interface Specification, V3.0, September 10, 1993. IEEE 1149.1, Standard Test Access Port and Boundary Scan Architecture, May 21, 1990. ITU (CCITT) Recommendation I.432, B-ISDN User-Network Interface - Physical Interface Specification, June 1990. UTOPIA, An ATM PHY Data Path Interface, Level 1, V2.01, February, 1994.
*
*
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
ORDERING INFORMATION Table 34 lists the ordering information.
Table 34. Ordering Information Part Number PM73488-PI Description 596-pin Enhanced Plastic Ball Grid Array (EPBGA) package
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
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NOTES
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PM73488 QSE 5 Gbit/s ATM Switch Fabric Element
Long Form Data Sheet
PMC-980616
Issue 3
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby B.C. Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: Corporate Information: Application Information: Web Site: document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness, or suitability for a particular purpose of any such information of the fitness or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PMC-980616 (R3) ref PMC-981002 (R2) Issue date: June 1999
137

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